Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

Roberto Sepúlveda; Oscar Montiel; José Olivas; Oscar Castillo

doi:10.1007/978-3-642-04514-1_17

Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

Roberto Sepúlveda, Oscar Montiel, José Olivas, Oscar Castillo

Centro de Investigación y Desarrollo de Tecnología Digital (CITEDI)

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

12 Scopus citations

Abstract

In this paper an improved high performance type-1 inference engine (IE) is proposed that can be applied with no modifications to the implementation of a type-2 FIS using the average method. The performance of the type-2 FIS will not be diminish for the use of this stage since it is achieved in parallel. The proposals are focused to be implemented into an FPGA. Simulink models to test the type-1 and type-2 inference engines are presented. The type-2 IE was tested in a speed controller for a DC motor.

Original language	English
Title of host publication	Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control
Editors	Oscar Castillo, Witold Pedrycz, Janusz Kacprzyk
Pages	295-308
Number of pages	14
DOIs	https://doi.org/10.1007/978-3-642-04514-1_17
State	Published - 2009

Publication series

Name	Studies in Computational Intelligence
Volume	257
ISSN (Print)	1860-949X

Access to Document

10.1007/978-3-642-04514-1_17

Cite this

Sepúlveda, R., Montiel, O., Olivas, J., & Castillo, O. (2009). Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. In O. Castillo, W. Pedrycz, & J. Kacprzyk (Eds.), Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control (pp. 295-308). (Studies in Computational Intelligence; Vol. 257). https://doi.org/10.1007/978-3-642-04514-1_17

Sepúlveda, Roberto ; Montiel, Oscar ; Olivas, José et al. / Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. editor / Oscar Castillo ; Witold Pedrycz ; Janusz Kacprzyk. 2009. pp. 295-308 (Studies in Computational Intelligence).

@inbook{9d6087ad9be04afaac4eafe70fa5173a,

title = "Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator",

abstract = "In this paper an improved high performance type-1 inference engine (IE) is proposed that can be applied with no modifications to the implementation of a type-2 FIS using the average method. The performance of the type-2 FIS will not be diminish for the use of this stage since it is achieved in parallel. The proposals are focused to be implemented into an FPGA. Simulink models to test the type-1 and type-2 inference engines are presented. The type-2 IE was tested in a speed controller for a DC motor.",

author = "Roberto Sep{\'u}lveda and Oscar Montiel and Jos{\'e} Olivas and Oscar Castillo",

year = "2009",

doi = "10.1007/978-3-642-04514-1_17",

language = "Ingl{\'e}s",

isbn = "9783642045134",

series = "Studies in Computational Intelligence",

pages = "295--308",

editor = "Oscar Castillo and Witold Pedrycz and Janusz Kacprzyk",

booktitle = "Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control",

}

Sepúlveda, R, Montiel, O, Olivas, J & Castillo, O 2009, Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. in O Castillo, W Pedrycz & J Kacprzyk (eds), Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. Studies in Computational Intelligence, vol. 257, pp. 295-308. https://doi.org/10.1007/978-3-642-04514-1_17

Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. / Sepúlveda, Roberto; Montiel, Oscar; Olivas, José et al.
Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. ed. / Oscar Castillo; Witold Pedrycz; Janusz Kacprzyk. 2009. p. 295-308 (Studies in Computational Intelligence; Vol. 257).

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

TY - CHAP

T1 - Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

AU - Sepúlveda, Roberto

AU - Montiel, Oscar

AU - Olivas, José

AU - Castillo, Oscar

PY - 2009

Y1 - 2009

N2 - In this paper an improved high performance type-1 inference engine (IE) is proposed that can be applied with no modifications to the implementation of a type-2 FIS using the average method. The performance of the type-2 FIS will not be diminish for the use of this stage since it is achieved in parallel. The proposals are focused to be implemented into an FPGA. Simulink models to test the type-1 and type-2 inference engines are presented. The type-2 IE was tested in a speed controller for a DC motor.

AB - In this paper an improved high performance type-1 inference engine (IE) is proposed that can be applied with no modifications to the implementation of a type-2 FIS using the average method. The performance of the type-2 FIS will not be diminish for the use of this stage since it is achieved in parallel. The proposals are focused to be implemented into an FPGA. Simulink models to test the type-1 and type-2 inference engines are presented. The type-2 IE was tested in a speed controller for a DC motor.

UR - http://www.scopus.com/inward/record.url?scp=70350180462&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-04514-1_17

DO - 10.1007/978-3-642-04514-1_17

M3 - Capítulo

AN - SCOPUS:70350180462

SN - 9783642045134

T3 - Studies in Computational Intelligence

SP - 295

EP - 308

BT - Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control

A2 - Castillo, Oscar

A2 - Pedrycz, Witold

A2 - Kacprzyk, Janusz

ER -

Sepúlveda R, Montiel O, Olivas J, Castillo O. Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. In Castillo O, Pedrycz W, Kacprzyk J, editors, Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. 2009. p. 295-308. (Studies in Computational Intelligence). doi: 10.1007/978-3-642-04514-1_17

Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

Abstract

Publication series

Access to Document

Other files and links

Fingerprint

Cite this