Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

Roberto Sepúlveda; Oscar Montiel; José Olivas; Oscar Castillo

doi:10.1007/978-3-642-04514-1_17

Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

Roberto Sepúlveda, Oscar Montiel, José Olivas, Oscar Castillo

Centro de Investigación y Desarrollo de Tecnología Digital (CITEDI)

Producción científica: Capítulo del libro/informe/acta de congreso › Capítulo › revisión exhaustiva

12 Citas (Scopus)

Resumen

In this paper an improved high performance type-1 inference engine (IE) is proposed that can be applied with no modifications to the implementation of a type-2 FIS using the average method. The performance of the type-2 FIS will not be diminish for the use of this stage since it is achieved in parallel. The proposals are focused to be implemented into an FPGA. Simulink models to test the type-1 and type-2 inference engines are presented. The type-2 IE was tested in a speed controller for a DC motor.

Idioma original	Inglés
Título de la publicación alojada	Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control
Editores	Oscar Castillo, Witold Pedrycz, Janusz Kacprzyk
Páginas	295-308
Número de páginas	14
DOI	https://doi.org/10.1007/978-3-642-04514-1_17
Estado	Publicada - 2009

Serie de la publicación

Nombre	Studies in Computational Intelligence
Volumen	257
ISSN (versión impresa)	1860-949X

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10.1007/978-3-642-04514-1_17

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Sepúlveda, R., Montiel, O., Olivas, J., & Castillo, O. (2009). Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. En O. Castillo, W. Pedrycz, & J. Kacprzyk (Eds.), Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control (pp. 295-308). (Studies in Computational Intelligence; Vol. 257). https://doi.org/10.1007/978-3-642-04514-1_17

Sepúlveda, Roberto ; Montiel, Oscar ; Olivas, José et al. / Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. editor / Oscar Castillo ; Witold Pedrycz ; Janusz Kacprzyk. 2009. pp. 295-308 (Studies in Computational Intelligence).

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Sepúlveda, R, Montiel, O, Olivas, J & Castillo, O 2009, Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. En O Castillo, W Pedrycz & J Kacprzyk (eds.), Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. Studies in Computational Intelligence, vol. 257, pp. 295-308. https://doi.org/10.1007/978-3-642-04514-1_17

Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. / Sepúlveda, Roberto; Montiel, Oscar; Olivas, José et al.
Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. ed. / Oscar Castillo; Witold Pedrycz; Janusz Kacprzyk. 2009. p. 295-308 (Studies in Computational Intelligence; Vol. 257).

Producción científica: Capítulo del libro/informe/acta de congreso › Capítulo › revisión exhaustiva

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Sepúlveda R, Montiel O, Olivas J, Castillo O. Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator. En Castillo O, Pedrycz W, Kacprzyk J, editores, Evolutionary Design of Intelligent Systems in Modeling, Simulation and Control. 2009. p. 295-308. (Studies in Computational Intelligence). doi: 10.1007/978-3-642-04514-1_17

Methodology to test and validate a VHDL inference engine of a type-2 FIS, through the xilinx system generator

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