FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

Thaimi Niubo-Aleman; José Ricardo Cardenas Valdez; José Alejandro Galaviz-Aguilar; J. Apolinar Reynoso-Hernandez; Manuel De Jesus García-Ortega; José Cruz Nuñez-Pérez

doi:10.1109/ROPEC.2015.7395116

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

Thaimi Niubo-Aleman, José Ricardo Cardenas Valdez, José Alejandro Galaviz-Aguilar, J. Apolinar Reynoso-Hernandez, Manuel De Jesus García-Ortega, José Cruz Nuñez-Pérez

Centro de Investigación y Desarrollo de Tecnología Digital (CITEDI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.

Original language	English
Title of host publication	2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467371216
DOIs	https://doi.org/10.1109/ROPEC.2015.7395116
State	Published - 29 Jan 2016
Event	17th IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015 - Ixtapa, Mexico Duration: 4 Nov 2015 → 6 Nov 2015

Publication series

Name	2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015

Conference

Conference	17th IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015
Country/Territory	Mexico
City	Ixtapa
Period	4/11/15 → 6/11/15

Keywords

FPGA
I/Q imbalance
constellation
power sensor

Access to Document

10.1109/ROPEC.2015.7395116

Cite this

Niubo-Aleman, T., Valdez, J. R. C., Galaviz-Aguilar, J. A., Reynoso-Hernandez, J. A., García-Ortega, M. D. J., & Nuñez-Pérez, J. C. (2016). FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. In 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015 Article 7395116 (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ROPEC.2015.7395116

Niubo-Aleman, Thaimi ; Valdez, José Ricardo Cardenas ; Galaviz-Aguilar, José Alejandro et al. / FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015).

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title = "FPGA-based design and implementation of a phase detector to correct the I/Q imbalance",

abstract = "This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.",

keywords = "FPGA, I/Q imbalance, constellation, power sensor",

author = "Thaimi Niubo-Aleman and Valdez, {Jos{\'e} Ricardo Cardenas} and Galaviz-Aguilar, {Jos{\'e} Alejandro} and Reynoso-Hernandez, {J. Apolinar} and Garc{\'i}a-Ortega, {Manuel De Jesus} and Nu{\~n}ez-P{\'e}rez, {Jos{\'e} Cruz}",

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year = "2016",

month = jan,

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doi = "10.1109/ROPEC.2015.7395116",

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Niubo-Aleman, T, Valdez, JRC, Galaviz-Aguilar, JA, Reynoso-Hernandez, JA, García-Ortega, MDJ & Nuñez-Pérez, JC 2016, FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. in 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015., 7395116, 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015, Institute of Electrical and Electronics Engineers Inc., 17th IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015, Ixtapa, Mexico, 4/11/15. https://doi.org/10.1109/ROPEC.2015.7395116

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. / Niubo-Aleman, Thaimi; Valdez, José Ricardo Cardenas; Galaviz-Aguilar, José Alejandro et al.
2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7395116 (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Niubo-Aleman, Thaimi

AU - Valdez, José Ricardo Cardenas

AU - Galaviz-Aguilar, José Alejandro

AU - Reynoso-Hernandez, J. Apolinar

AU - García-Ortega, Manuel De Jesus

AU - Nuñez-Pérez, José Cruz

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Y1 - 2016/1/29

N2 - This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.

AB - This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.

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BT - 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015

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Niubo-Aleman T, Valdez JRC, Galaviz-Aguilar JA, Reynoso-Hernandez JA, García-Ortega MDJ, Nuñez-Pérez JC. FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. In 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7395116. (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015). doi: 10.1109/ROPEC.2015.7395116

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

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Keywords

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