FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

Thaimi Niubo-Aleman; José Ricardo Cardenas Valdez; José Alejandro Galaviz-Aguilar; J. Apolinar Reynoso-Hernandez; Manuel De Jesus García-Ortega; José Cruz Nuñez-Pérez

doi:10.1109/ROPEC.2015.7395116

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

Thaimi Niubo-Aleman, José Ricardo Cardenas Valdez, José Alejandro Galaviz-Aguilar, J. Apolinar Reynoso-Hernandez, Manuel De Jesus García-Ortega, José Cruz Nuñez-Pérez

Centro de Investigación y Desarrollo de Tecnología Digital (CITEDI)

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.

Idioma original	Inglés
Título de la publicación alojada	2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015
Editorial	Institute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)	9781467371216
DOI	https://doi.org/10.1109/ROPEC.2015.7395116
Estado	Publicada - 29 ene. 2016
Evento	17th IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015 - Ixtapa, México Duración: 4 nov. 2015 → 6 nov. 2015

Serie de la publicación

Nombre	2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015

Conferencia

Conferencia	17th IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015
País/Territorio	México
Ciudad	Ixtapa
Período	4/11/15 → 6/11/15

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10.1109/ROPEC.2015.7395116

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Niubo-Aleman, T., Valdez, J. R. C., Galaviz-Aguilar, J. A., Reynoso-Hernandez, J. A., García-Ortega, M. D. J., & Nuñez-Pérez, J. C. (2016). FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. En 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015 Artículo 7395116 (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ROPEC.2015.7395116

Niubo-Aleman, Thaimi ; Valdez, José Ricardo Cardenas ; Galaviz-Aguilar, José Alejandro et al. / FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015).

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title = "FPGA-based design and implementation of a phase detector to correct the I/Q imbalance",

abstract = "This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.",

keywords = "FPGA, I/Q imbalance, constellation, power sensor",

author = "Thaimi Niubo-Aleman and Valdez, {Jos{\'e} Ricardo Cardenas} and Galaviz-Aguilar, {Jos{\'e} Alejandro} and Reynoso-Hernandez, {J. Apolinar} and Garc{\'i}a-Ortega, {Manuel De Jesus} and Nu{\~n}ez-P{\'e}rez, {Jos{\'e} Cruz}",

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year = "2016",

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doi = "10.1109/ROPEC.2015.7395116",

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Niubo-Aleman, T, Valdez, JRC, Galaviz-Aguilar, JA, Reynoso-Hernandez, JA, García-Ortega, MDJ & Nuñez-Pérez, JC 2016, FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. En 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015., 7395116, 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015, Institute of Electrical and Electronics Engineers Inc., 17th IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015, Ixtapa, México, 4/11/15. https://doi.org/10.1109/ROPEC.2015.7395116

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. / Niubo-Aleman, Thaimi; Valdez, José Ricardo Cardenas; Galaviz-Aguilar, José Alejandro et al.
2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7395116 (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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AU - Niubo-Aleman, Thaimi

AU - Valdez, José Ricardo Cardenas

AU - Galaviz-Aguilar, José Alejandro

AU - Reynoso-Hernandez, J. Apolinar

AU - García-Ortega, Manuel De Jesus

AU - Nuñez-Pérez, José Cruz

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N2 - This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.

AB - This paper describes the design and implementation of a system to evaluate the I/Q modulation when phase and amplitude imperfections are added. This system allows observing the signal behavior in the presence of phase and amplitude imbalance. An approach to correct I/Q imbalances using a power detector is proposed, by means calculating peak impairments in the interest signal and phase shifting is detected. Phase shift stability is introduced for correcting (I or Q) branches respectively to guarantee amplitude and phase balancing condition in the modulator output. Experimental results are implemented employing an FPGA by using DSP-Builder to bit true VHDL hardware description of proposed model. The modulated signal with the constellation and measurements in the oscilloscope is compared.

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Niubo-Aleman T, Valdez JRC, Galaviz-Aguilar JA, Reynoso-Hernandez JA, García-Ortega MDJ, Nuñez-Pérez JC. FPGA-based design and implementation of a phase detector to correct the I/Q imbalance. En 2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7395116. (2015 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2015). doi: 10.1109/ROPEC.2015.7395116

FPGA-based design and implementation of a phase detector to correct the I/Q imbalance

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