Design and simulation of the fuzzification stage through the Xilinx system generator

Yazmín Maldonado, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

14 Scopus citations

Abstract

In the last years, several algorithms to implement the fuzzification stage for Very Large Scale of Integration (VLSI) Integrated Circuits (IC) using a Hardware Description Language (HDL) have been developed. In this work it is presented a proposal based in the arithmetic calculation of the slopes in triangular and trapezoidal membership functions to obtain a fuzzified value. We used an arithmetic calculation algorithm to implement trapezoidal and triangular membership functions. This proposal is different to others that at present time are currently used. We discuss the advantages and disadvantages of this implementation. A methodology to test and validate this stage through the Xilinx System Generator is described.

Original languageEnglish
Title of host publicationSoft Computing for Hybrid Intelligent Systems
EditorsOscar Castillo, Patricia Melin, Janusz Kacprzyk, Witold Pedrycz
Pages297-305
Number of pages9
DOIs
StatePublished - 22 Sep 2008

Publication series

NameStudies in Computational Intelligence
Volume154
ISSN (Print)1860-949X

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