Design and simulation of the fuzzification stage through the Xilinx system generator

Yazmín Maldonado, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo

Producción científica: Capítulo del libro/informe/acta de congresoCapítulorevisión exhaustiva

14 Citas (Scopus)

Resumen

In the last years, several algorithms to implement the fuzzification stage for Very Large Scale of Integration (VLSI) Integrated Circuits (IC) using a Hardware Description Language (HDL) have been developed. In this work it is presented a proposal based in the arithmetic calculation of the slopes in triangular and trapezoidal membership functions to obtain a fuzzified value. We used an arithmetic calculation algorithm to implement trapezoidal and triangular membership functions. This proposal is different to others that at present time are currently used. We discuss the advantages and disadvantages of this implementation. A methodology to test and validate this stage through the Xilinx System Generator is described.

Idioma originalInglés
Título de la publicación alojadaSoft Computing for Hybrid Intelligent Systems
EditoresOscar Castillo, Patricia Melin, Janusz Kacprzyk, Witold Pedrycz
Páginas297-305
Número de páginas9
DOI
EstadoPublicada - 22 sep. 2008

Serie de la publicación

NombreStudies in Computational Intelligence
Volumen154
ISSN (versión impresa)1860-949X

Huella

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