A symmetrical, arbitrary factor frequency divider: An example of non-pulse-mode sequential circuits

The work here presented is based on the experience of teaching digital circuits at both, undergraduate and graduate levels, at the National Polytechnic Institute, Campus Culhuacan in Mexico City. We describe the design of a circuit used to divide the frequency of an square signal by an arbitrary factor n, but with the additional restriction that the resulting signal must be symmetrical. When the factor is a power of two the solution is almost trivial, but for odd or non power of two factors (3, 5, 6, 7, 11, 18, etc.) the problem must be solved using non-pulse-mode circuits. Based on a previous work [2], we present a general circuit that was implemented and tested without problems in an FPGA, using available free University Program tools.