TY - GEN
T1 - Voltage source circuit based on CMOS floating-gate memory
AU - De La Cruz Alejo, Jesús
AU - Ponce, Victor
AU - Castañeda, Felipe Gómez
AU - Cadenas, José A.Moreno
PY - 2007
Y1 - 2007
N2 - This paper present a new circuit designed to support high accuracy reference voltages over a nearly full range of the power supply. To achieve this, the circuit is designed to be efficient utilizing a CMOS floating gate memory fabricated in 1.2 μm CMOS process. The memory stores voltages as charge on the floating gate of a pMOS transistor. The output voltages of the circuit are easily programming by simply modifying the value of the floating gate through the tunnelling and injection hot electrons mechanisms. Also, the circuit can drive a resistive load with the advantage of reduced both silicon area and dissipated power on chip.
AB - This paper present a new circuit designed to support high accuracy reference voltages over a nearly full range of the power supply. To achieve this, the circuit is designed to be efficient utilizing a CMOS floating gate memory fabricated in 1.2 μm CMOS process. The memory stores voltages as charge on the floating gate of a pMOS transistor. The output voltages of the circuit are easily programming by simply modifying the value of the floating gate through the tunnelling and injection hot electrons mechanisms. Also, the circuit can drive a resistive load with the advantage of reduced both silicon area and dissipated power on chip.
KW - CMOS
KW - Floating gate
KW - Injection
KW - Tunneling
UR - http://www.scopus.com/inward/record.url?scp=49749107623&partnerID=8YFLogxK
U2 - 10.1109/ICEEE.2007.4345050
DO - 10.1109/ICEEE.2007.4345050
M3 - Contribución a la conferencia
AN - SCOPUS:49749107623
SN - 1424411661
SN - 9781424411665
T3 - 2007 4th International Conference on Electrical and Electronics Engineering, ICEEE 2007
SP - 400
EP - 403
BT - 2007 4th International Conference on Electrical and Electronics Engineering, ICEEE 2007
T2 - 2007 4th International Conference on Electrical and Electronics Engineering, ICEEE 2007
Y2 - 5 September 2007 through 7 September 2007
ER -