FPGA implementations for chaotic maps using fixed-point and floating-point representations

This work presents the implementation of various chaotic maps; among the maps there are one-dimensional and two-dimensional ones. In order to implement the maps, their mathematical descriptions are modified to be represented with more accuracy by different binary representations. The sequences from the same map are compared to determine until which iteration, different descriptions produce similar outputs. The similarity coefficient is established in five percent. Comparison delivers some interesting findings; first, the one-dimensional maps, in this work, have comparative number of similar iterations. Second, the bi-dimensional maps present the lowest and highest number of similar iterations. Based on the modified mathematical descriptions, the VHDL implementations are developed. They are simulated and their results are compared against the modified mathematical description ones; resulting that both groups of results are congruent.