FPGA implementations for chaotic maps using fixed-point and floating-point representations

Ricardo Francisco Martinez-Gonzalez, Jose Alejandro Diaz-Mendez, Ruben Vazquez-Medina, Juan Lopez-Hernandez

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review

1 Scopus citations

Abstract

This work presents the implementation of various chaotic maps; among the maps there are one-dimensional and two-dimensional ones. In order to implement the maps, their mathematical descriptions are modified to be represented with more accuracy by different binary representations. The sequences from the same map are compared to determine until which iteration, different descriptions produce similar outputs. The similarity coefficient is established in five percent. Comparison delivers some interesting findings; first, the one-dimensional maps, in this work, have comparative number of similar iterations. Second, the bi-dimensional maps present the lowest and highest number of similar iterations. Based on the modified mathematical descriptions, the VHDL implementations are developed. They are simulated and their results are compared against the modified mathematical description ones; resulting that both groups of results are congruent.

Original languageEnglish
Title of host publicationField-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation
PublisherIGI Global
Pages59-97
Number of pages39
ISBN (Electronic)9781522503002
ISBN (Print)1522502998, 9781522502999
DOIs
StatePublished - 5 Jul 2016

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