Finite field polynomial 16-bit multiplier for power constrained devices

José Antonio Flores Escobar; Moisés Salinas Rosales; José Velázquez López

doi:10.1109/CONIELECOMP.2012.6189902

Finite field polynomial 16-bit multiplier for power constrained devices

José Antonio Flores Escobar, Moisés Salinas Rosales, José Velázquez López

Centro de Investigación en Computación (CIC)

Producción científica: Contribución a una conferencia › Artículo › revisión exhaustiva

Resumen

In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.

Idioma original	Inglés
Páginas	162-167
Número de páginas	6
DOI	https://doi.org/10.1109/CONIELECOMP.2012.6189902
Estado	Publicada - 2012
Evento	22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012 - Cholula, México Duración: 27 feb. 2012 → 29 feb. 2012

Conferencia

Conferencia	22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012
País/Territorio	México
Ciudad	Cholula
Período	27/02/12 → 29/02/12

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10.1109/CONIELECOMP.2012.6189902

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title = "Finite field polynomial 16-bit multiplier for power constrained devices",

abstract = "In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.",

author = "Escobar, {Jos{\'e} Antonio Flores} and Rosales, {Mois{\'e}s Salinas} and L{\'o}pez, {Jos{\'e} Vel{\'a}zquez}",

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doi = "10.1109/CONIELECOMP.2012.6189902",

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Finite field polynomial 16-bit multiplier for power constrained devices. / Escobar, José Antonio Flores; Rosales, Moisés Salinas; López, José Velázquez.
2012. 162-167 Papel presentado en 22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012, Cholula, México.

Producción científica: Contribución a una conferencia › Artículo › revisión exhaustiva

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AU - Rosales, Moisés Salinas

AU - López, José Velázquez

PY - 2012

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AB - In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.

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DO - 10.1109/CONIELECOMP.2012.6189902

M3 - Artículo

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T2 - 22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012

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Finite field polynomial 16-bit multiplier for power constrained devices

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