Finite field polynomial 16-bit multiplier for power constrained devices

José Antonio Flores Escobar; Moisés Salinas Rosales; José Velázquez López

doi:10.1109/CONIELECOMP.2012.6189902

Finite field polynomial 16-bit multiplier for power constrained devices

José Antonio Flores Escobar, Moisés Salinas Rosales, José Velázquez López

Centro de Investigación en Computación (CIC)

Research output: Contribution to conference › Paper › peer-review

Abstract

In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.

Original language	English
Pages	162-167
Number of pages	6
DOIs	https://doi.org/10.1109/CONIELECOMP.2012.6189902
State	Published - 2012
Event	22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012 - Cholula, Mexico Duration: 27 Feb 2012 → 29 Feb 2012

Conference

Conference	22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012
Country/Territory	Mexico
City	Cholula
Period	27/02/12 → 29/02/12

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10.1109/CONIELECOMP.2012.6189902

Cite this

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title = "Finite field polynomial 16-bit multiplier for power constrained devices",

abstract = "In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.",

author = "Escobar, {Jos{\'e} Antonio Flores} and Rosales, {Mois{\'e}s Salinas} and L{\'o}pez, {Jos{\'e} Vel{\'a}zquez}",

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doi = "10.1109/CONIELECOMP.2012.6189902",

language = "Ingl{\'e}s",

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Finite field polynomial 16-bit multiplier for power constrained devices. / Escobar, José Antonio Flores; Rosales, Moisés Salinas; López, José Velázquez.
2012. 162-167 Paper presented at 22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012, Cholula, Mexico.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

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AU - Rosales, Moisés Salinas

AU - López, José Velázquez

PY - 2012

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DO - 10.1109/CONIELECOMP.2012.6189902

M3 - Artículo

AN - SCOPUS:84862098148

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T2 - 22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012

Y2 - 27 February 2012 through 29 February 2012

ER -

Finite field polynomial 16-bit multiplier for power constrained devices

Abstract

Conference

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