Decreasing the V_th shift of InGaZnO thin-film transistors under positive and negative bias stress using SU-8 as etch-stop and passivation layer

In order to expand the InGaZnO (IGZO) technology to several applications other than displays, including integrated circuits with certain complexity, it is necessary to mitigate the V_th shift under bias stress. For this purpose, the use of a passivated semiconductor channel has demonstrated its effectiveness in improving the V_th reliability. In this work, staggered bottom gate IGZO thin-film transistors were fabricated using a 450 nm SU-8 2000.5 film as a passivation and etch-stop layer. The thin-film transistors (TFTs) were fabricated by a full lithography process and the SU-8 film determined the maximum processing temperature of 200 ^◦C. Positive and negative bias stress were performed during 1200 s on 150 µm/40 µm (W/L) TFTs stressed at low field (2 MV cm^-1) and high field (4 MV cm^-1) leading to a maximum V_th shift of 0.12 V and -0.38 V, respectively. The negative V_th shift was associated to an undesired mechanism dominated by hydrogen migration. The spin coated SU-8 passivation layer demonstrated higher device stability and it can be also used for future interconnection between transistors.