A new pointer-based instruction queue design and its power-performance evaluation

Marco A. Ramírez; Adrian Cristal; Alexander V. Veidenbaum; Luis Villa; Mateo Valero

doi:10.1109/ICCD.2005.12

A new pointer-based instruction queue design and its power-performance evaluation

Marco A. Ramírez, Adrian Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero

Centro de Investigación en Computación (CIC)

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

5 Citas (Scopus)

Resumen

Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

Idioma original	Inglés
Título de la publicación alojada	Proceedings - 2005 IEEE International Conference on Computer Design
Subtítulo de la publicación alojada	VLSI in Computers and Processors, ICCD 2005
Páginas	647-653
Número de páginas	7
DOI	https://doi.org/10.1109/ICCD.2005.12
Estado	Publicada - 2005
Evento	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, Estados Unidos Duración: 2 oct. 2005 → 5 oct. 2005

Serie de la publicación

Nombre	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volumen	2005
ISSN (versión impresa)	1063-6404

Conferencia

Conferencia	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
País/Territorio	Estados Unidos
Ciudad	San Jose, CA
Período	2/10/05 → 5/10/05

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

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10.1109/ICCD.2005.12

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Ramírez, M. A., Cristal, A., Veidenbaum, A. V., Villa, L., & Valero, M. (2005). A new pointer-based instruction queue design and its power-performance evaluation. En Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 647-653). Artículo 1524220 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.12

Ramírez, Marco A. ; Cristal, Adrian ; Veidenbaum, Alexander V. et al. / A new pointer-based instruction queue design and its power-performance evaluation. Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. pp. 647-653 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

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title = "A new pointer-based instruction queue design and its power-performance evaluation",

abstract = "Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.",

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Ramírez, MA, Cristal, A, Veidenbaum, AV, Villa, L & Valero, M 2005, A new pointer-based instruction queue design and its power-performance evaluation. En Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005., 1524220, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2005, pp. 647-653, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, Estados Unidos, 2/10/05. https://doi.org/10.1109/ICCD.2005.12

A new pointer-based instruction queue design and its power-performance evaluation. / Ramírez, Marco A.; Cristal, Adrian; Veidenbaum, Alexander V. et al.
Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 647-653 1524220 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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T1 - A new pointer-based instruction queue design and its power-performance evaluation

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AU - Cristal, Adrian

AU - Veidenbaum, Alexander V.

AU - Villa, Luis

AU - Valero, Mateo

PY - 2005

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N2 - Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

AB - Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

KW - CAM

KW - Instruction Wakeup

KW - Issue Queue

KW - Low Power

KW - Out-of-Order Processors

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Ramírez MA, Cristal A, Veidenbaum AV, Villa L, Valero M. A new pointer-based instruction queue design and its power-performance evaluation. En Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 647-653. 1524220. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD.2005.12

A new pointer-based instruction queue design and its power-performance evaluation

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