A new pointer-based instruction queue design and its power-performance evaluation

Marco A. Ramírez; Adrian Cristal; Alexander V. Veidenbaum; Luis Villa; Mateo Valero

doi:10.1109/ICCD.2005.12

A new pointer-based instruction queue design and its power-performance evaluation

Marco A. Ramírez, Adrian Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero

Centro de Investigación en Computación (CIC)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

Original language	English
Title of host publication	Proceedings - 2005 IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2005
Pages	647-653
Number of pages	7
DOIs	https://doi.org/10.1109/ICCD.2005.12
State	Published - 2005
Event	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States Duration: 2 Oct 2005 → 5 Oct 2005

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Volume	2005
ISSN (Print)	1063-6404

Conference

Conference	2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Country/Territory	United States
City	San Jose, CA
Period	2/10/05 → 5/10/05

Keywords

CAM
Instruction Wakeup
Issue Queue
Low Power
Out-of-Order Processors

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ICCD.2005.12

Cite this

Ramírez, M. A., Cristal, A., Veidenbaum, A. V., Villa, L., & Valero, M. (2005). A new pointer-based instruction queue design and its power-performance evaluation. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 (pp. 647-653). Article 1524220 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005). https://doi.org/10.1109/ICCD.2005.12

Ramírez, Marco A. ; Cristal, Adrian ; Veidenbaum, Alexander V. et al. / A new pointer-based instruction queue design and its power-performance evaluation. Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. pp. 647-653 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

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title = "A new pointer-based instruction queue design and its power-performance evaluation",

abstract = "Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.",

keywords = "CAM, Instruction Wakeup, Issue Queue, Low Power, Out-of-Order Processors",

author = "Ram{\'i}rez, {Marco A.} and Adrian Cristal and Veidenbaum, {Alexander V.} and Luis Villa and Mateo Valero",

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Ramírez, MA, Cristal, A, Veidenbaum, AV, Villa, L & Valero, M 2005, A new pointer-based instruction queue design and its power-performance evaluation. in Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005., 1524220, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, vol. 2005, pp. 647-653, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, United States, 2/10/05. https://doi.org/10.1109/ICCD.2005.12

A new pointer-based instruction queue design and its power-performance evaluation. / Ramírez, Marco A.; Cristal, Adrian; Veidenbaum, Alexander V. et al.
Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 647-653 1524220 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A new pointer-based instruction queue design and its power-performance evaluation

AU - Ramírez, Marco A.

AU - Cristal, Adrian

AU - Veidenbaum, Alexander V.

AU - Villa, Luis

AU - Valero, Mateo

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N2 - Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

AB - Instruction queues consume a significant amount of power in a high-performance processor. The wakeup logic delay is also a critical timing parameter. This paper compares a commonly used CAM-based instruction queue organization with a new pointer-based design for delay and energy efficiency. A design and pre-layout of all critical structures in 70nm technology is performed for both organizations. The pointerbased design is shown to use 10 to 15 times less power than the CAM-based design, depending on queue size, for a 4-wide issue, SGHz processor. The results also demonstrate the importance of evaluating all steps of instruction queue access: allocation, issue and wakeup rather than wakeup alone, especially for power consumption.

KW - CAM

KW - Instruction Wakeup

KW - Issue Queue

KW - Low Power

KW - Out-of-Order Processors

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M3 - Contribución a la conferencia

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Ramírez MA, Cristal A, Veidenbaum AV, Villa L, Valero M. A new pointer-based instruction queue design and its power-performance evaluation. In Proceedings - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005. 2005. p. 647-653. 1524220. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). doi: 10.1109/ICCD.2005.12

A new pointer-based instruction queue design and its power-performance evaluation

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Keywords

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