Stride-based speculative cache access

Luis Villa; Oscar Camacho; Alejandro Villar; Cesar Osuna; Gustavo Santana; Manuel Romero

Stride-based speculative cache access

Luis Villa, Oscar Camacho, Alejandro Villar, Cesar Osuna, Gustavo Santana, Manuel Romero

Centro de Innovación y Desarrollo Tecnológico en Cómputo (CIDETEC)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Serialized cache access has been a strategy proposed in others' works to reduce the latency penalty introduced in a two-way set-associative cache. In this paper we present a novel mechanism, which provides a better or the same miss rate as a two-way set-associative cache, and with similar access time as a direct mapped cache. We use an address prediction strategy to select the correct cache set-entry in a virtually partitioned direct mapped cache.

Original language	English
Title of host publication	Proceedings of the IASTED International Conference on Computer Science and Technology
Editors	S. Sahni
Pages	164-169
Number of pages	6
State	Published - 2003
Event	Proceedings of the IASTED International Conference on Computer Science and Technology - Cancun, Mexico Duration: 19 May 2003 → 21 May 2003

Publication series

Name	Proceedings of the IASTED International Conference on Computer Science and Technology

Conference

Conference	Proceedings of the IASTED International Conference on Computer Science and Technology
Country/Territory	Mexico
City	Cancun
Period	19/05/03 → 21/05/03

Keywords

Cache
Memory
Prediction
Speculative

Cite this

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title = "Stride-based speculative cache access",

abstract = "Serialized cache access has been a strategy proposed in others' works to reduce the latency penalty introduced in a two-way set-associative cache. In this paper we present a novel mechanism, which provides a better or the same miss rate as a two-way set-associative cache, and with similar access time as a direct mapped cache. We use an address prediction strategy to select the correct cache set-entry in a virtually partitioned direct mapped cache.",

keywords = "Cache, Memory, Prediction, Speculative",

author = "Luis Villa and Oscar Camacho and Alejandro Villar and Cesar Osuna and Gustavo Santana and Manuel Romero",

year = "2003",

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series = "Proceedings of the IASTED International Conference on Computer Science and Technology",

pages = "164--169",

editor = "S. Sahni",

booktitle = "Proceedings of the IASTED International Conference on Computer Science and Technology",

note = "Proceedings of the IASTED International Conference on Computer Science and Technology ; Conference date: 19-05-2003 Through 21-05-2003",

}

Villa, L, Camacho, O, Villar, A, Osuna, C, Santana, G & Romero, M 2003, Stride-based speculative cache access. in S Sahni (ed.), Proceedings of the IASTED International Conference on Computer Science and Technology. Proceedings of the IASTED International Conference on Computer Science and Technology, pp. 164-169, Proceedings of the IASTED International Conference on Computer Science and Technology, Cancun, Mexico, 19/05/03.

Stride-based speculative cache access. / Villa, Luis; Camacho, Oscar; Villar, Alejandro et al.
Proceedings of the IASTED International Conference on Computer Science and Technology. ed. / S. Sahni. 2003. p. 164-169 (Proceedings of the IASTED International Conference on Computer Science and Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Stride-based speculative cache access

AU - Villa, Luis

AU - Camacho, Oscar

AU - Villar, Alejandro

AU - Osuna, Cesar

AU - Santana, Gustavo

AU - Romero, Manuel

PY - 2003

Y1 - 2003

N2 - Serialized cache access has been a strategy proposed in others' works to reduce the latency penalty introduced in a two-way set-associative cache. In this paper we present a novel mechanism, which provides a better or the same miss rate as a two-way set-associative cache, and with similar access time as a direct mapped cache. We use an address prediction strategy to select the correct cache set-entry in a virtually partitioned direct mapped cache.

AB - Serialized cache access has been a strategy proposed in others' works to reduce the latency penalty introduced in a two-way set-associative cache. In this paper we present a novel mechanism, which provides a better or the same miss rate as a two-way set-associative cache, and with similar access time as a direct mapped cache. We use an address prediction strategy to select the correct cache set-entry in a virtually partitioned direct mapped cache.

KW - Cache

KW - Memory

KW - Prediction

KW - Speculative

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M3 - Contribución a la conferencia

AN - SCOPUS:1542432864

SN - 0889863490

T3 - Proceedings of the IASTED International Conference on Computer Science and Technology

SP - 164

EP - 169

BT - Proceedings of the IASTED International Conference on Computer Science and Technology

A2 - Sahni, S.

T2 - Proceedings of the IASTED International Conference on Computer Science and Technology

Y2 - 19 May 2003 through 21 May 2003

ER -

Stride-based speculative cache access

Abstract

Publication series

Conference

Keywords

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