Simple improvement stage for low voltage WTA and rank order circuits

Jesus E. Molinar-Solis; Rodolfo Garcia-Lozano; Alejandra Morales-Ramirez; Jaime Ramirez-Angulo

doi:10.1109/ISCAS.2011.5937708

Simple improvement stage for low voltage WTA and rank order circuits

Jesus E. Molinar-Solis, Rodolfo Garcia-Lozano, Alejandra Morales-Ramirez, Jaime Ramirez-Angulo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A simple improvement to Lazzaro's Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. A low voltage Rank Order Filter is derived from the WTA using current starving techniques. Electrical measurements of a prototype in CMOS 0.5m technology verify the operation of the WTA circuit with V_DD = 1.5V. Simulations in PSpice show the functionality of a Rank Order Circuit using the same principle.

Original language	English
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	885-888
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937708
State	Published - 2011
Externally published	Yes
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: 15 May 2011 → 18 May 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	15/05/11 → 18/05/11

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10.1109/ISCAS.2011.5937708

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Molinar-Solis, J. E., Garcia-Lozano, R., Morales-Ramirez, A., & Ramirez-Angulo, J. (2011). Simple improvement stage for low voltage WTA and rank order circuits. In 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 (pp. 885-888). Article 5937708 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2011.5937708

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title = "Simple improvement stage for low voltage WTA and rank order circuits",

abstract = "A simple improvement to Lazzaro's Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. A low voltage Rank Order Filter is derived from the WTA using current starving techniques. Electrical measurements of a prototype in CMOS 0.5m technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice show the functionality of a Rank Order Circuit using the same principle.",

author = "Molinar-Solis, {Jesus E.} and Rodolfo Garcia-Lozano and Alejandra Morales-Ramirez and Jaime Ramirez-Angulo",

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Molinar-Solis, JE, Garcia-Lozano, R, Morales-Ramirez, A & Ramirez-Angulo, J 2011, Simple improvement stage for low voltage WTA and rank order circuits. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937708, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 885-888, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 15/05/11. https://doi.org/10.1109/ISCAS.2011.5937708

Simple improvement stage for low voltage WTA and rank order circuits. / Molinar-Solis, Jesus E.; Garcia-Lozano, Rodolfo; Morales-Ramirez, Alejandra et al.
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. 2011. p. 885-888 5937708 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Garcia-Lozano, Rodolfo

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PY - 2011

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AB - A simple improvement to Lazzaro's Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. A low voltage Rank Order Filter is derived from the WTA using current starving techniques. Electrical measurements of a prototype in CMOS 0.5m technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice show the functionality of a Rank Order Circuit using the same principle.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011

Y2 - 15 May 2011 through 18 May 2011

ER -

Simple improvement stage for low voltage WTA and rank order circuits

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