Design and simulation of the type-2 fuzzification stage: Using active membership functions

This paper describes the design and implementation of the fuzzification stage for type-1 and type-2 fuzzy inference systems (FIS). A versatile method to calculate the membership values was used, it handles real numbers using decimal floating point binary encoding to calculate the slopes of triangular and trapezoidal membership functions. The designs were developed using VHDL code for FPGA implementation. The type-1 implementation is shown to give the basis of the type-2 implementation, which is based on the average method that consists in substituting an interval type-2 FIS by two type-1 FISs to cope with uncertainty. The functionality of the designs were evaluated by the analysis of the control surface plots of a speed controller for a DC motor. The plots were obtained from Simulink models that includes the VHDL designs developed in the Xilinx ISE. They were imported to the Simulink environment through the Xilinx System Generator.