Abstract
The aim of this work is the design and implementation of a DWT architecture FPGA-based platform for up to three dimensional signal processing. First, filter banks are designed using a distributed arithmetic technique. Then, we design controllers, interfaces and protocols that handle, transmit and sequence all the data during the computing process. Data is sent via USB to the FPGA and the user interface is programmed in MATLAB. A graphical user interface manages the system operation and displays the results on a PC. Designed filters are compared with a fully parallel architecture in relation to the number of gates used, speed, and algorithm performance.
Original language | English |
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Pages | 333-338 |
Number of pages | 6 |
DOIs | |
State | Published - 2012 |
Externally published | Yes |
Event | 22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012 - Cholula, Mexico Duration: 27 Feb 2012 → 29 Feb 2012 |
Conference
Conference | 22nd Annual International Conference on Electronics, Communications and Computers, CONIELECOMP 2012 |
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Country/Territory | Mexico |
City | Cholula |
Period | 27/02/12 → 29/02/12 |
Keywords
- Daubechies
- Distributed Arithmetic
- Filter Design