Bias-stress instabilities in low-temperature thin-film transistors made of Al₂O₃ and ZnO films deposited by PEALD

Thin film transistors (TFT) were fabricated by plasma-enhanced atomic layer deposition (PE-ALD) of aluminum oxide (Al₂O₃) and zinc oxide (ZnO) on glass substrates at 70 °C. The thicknesses of the Al₂O₃ (gate dielectric) and ZnO (n-type semiconductor) were 25 and 60 nm, respectively. Prior to Al₂O₃ deposition Cr/Au gate contacts were patterned using photolithography. Photolithography was also used to define aluminum source and drain contacts with thickness of 200 nm. The W/L ratio of the fabricated transistors was varied between 1 and 8 by varying the channel length L (40, 20 10 and 5 μm), while the channel width W was kept constant to 40 μm. Capacitance-voltage measurements revealed good uniformity of the Al₂O₃ layer with a dielectric constant value of ~8. The sheet resistance of the ZnO layer was found to be ~2400 Ω/sq. The TFT electrical characterization showed that the saturation mobility does not depend substantially on W/L ratio and had values between 0.82 and 1.1 cm²/V-s, while the subthreshold slope varied between 190 and 207 mV/dec. Moreover, a high on/off current ratio of ⁓10⁷ was determined. The threshold voltage (V_th) instability was also characterized by positive and negative bias stress leading to a V_th shift of about −0.3 V and − 0.8 V, respectively.