TY - GEN
T1 - Automatic code generator for a customized high performance microprocessor simulator
AU - Cristóbal-Salas, Alfredo
AU - Santiago-Domínguez, Juan D.
AU - Santiago-Vicente, Bardo
AU - Ramírez-Salinas, Marco Antonio
AU - Villa-Vargas, Luis Alfonso
AU - Layva-Santes, Neiel Israel
AU - Hernández-Calderón, Cesar Alejandro
AU - Rojas-Morales, Carlos
N1 - Publisher Copyright:
© Springer Nature Switzerland AG 2019.
PY - 2019
Y1 - 2019
N2 - This paper presents a software that generates code that implements a microprocessor simulator based on features defined by user. Software receives a set of microprocessor architecture description that includes: number of cores, operations to be executed in the ALU, cache memory details, and number of registers, among others. After configuration, the software generates Java code that implements the microprocessor simulator described. Software can generates more than forty different codes depending on the configurations defined. Each simulator follows a standard four stages pipeline: fetch, decode, execute and store. Code generator has been used as a learning tool in an undergraduate course with interesting effects in the student’s learning process. Preliminary results show that students understand better how a microprocessor works and they felt ready to propose new microprocessor architectures.
AB - This paper presents a software that generates code that implements a microprocessor simulator based on features defined by user. Software receives a set of microprocessor architecture description that includes: number of cores, operations to be executed in the ALU, cache memory details, and number of registers, among others. After configuration, the software generates Java code that implements the microprocessor simulator described. Software can generates more than forty different codes depending on the configurations defined. Each simulator follows a standard four stages pipeline: fetch, decode, execute and store. Code generator has been used as a learning tool in an undergraduate course with interesting effects in the student’s learning process. Preliminary results show that students understand better how a microprocessor works and they felt ready to propose new microprocessor architectures.
KW - Architecture
KW - Code generator
KW - ISA
KW - Microprocessor
KW - Simulator
UR - http://www.scopus.com/inward/record.url?scp=85059912345&partnerID=8YFLogxK
U2 - 10.1007/978-3-030-10448-1_2
DO - 10.1007/978-3-030-10448-1_2
M3 - Contribución a la conferencia
SN - 9783030104474
T3 - Communications in Computer and Information Science
SP - 11
EP - 23
BT - Supercomputing - 9th International Conference, ISUM 2018, Revised Selected Papers
A2 - Gitler, Isidoro
A2 - Klapp, Jaime
A2 - Tchernykh, Andrei
A2 - Torres, Moises
PB - Springer Verlag
T2 - 9th International Conference on Supercomputing, ISUM 2018
Y2 - 5 March 2018 through 9 March 2018
ER -