Automatic code generator for a customized high performance microprocessor simulator

Alfredo Cristóbal-Salas, Juan D. Santiago-Domínguez, Bardo Santiago-Vicente, Marco Antonio Ramírez-Salinas, Luis Alfonso Villa-Vargas, Neiel Israel Layva-Santes, Cesar Alejandro Hernández-Calderón, Carlos Rojas-Morales

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

Resumen

This paper presents a software that generates code that implements a microprocessor simulator based on features defined by user. Software receives a set of microprocessor architecture description that includes: number of cores, operations to be executed in the ALU, cache memory details, and number of registers, among others. After configuration, the software generates Java code that implements the microprocessor simulator described. Software can generates more than forty different codes depending on the configurations defined. Each simulator follows a standard four stages pipeline: fetch, decode, execute and store. Code generator has been used as a learning tool in an undergraduate course with interesting effects in the student’s learning process. Preliminary results show that students understand better how a microprocessor works and they felt ready to propose new microprocessor architectures.

Idioma originalInglés
Título de la publicación alojadaSupercomputing - 9th International Conference, ISUM 2018, Revised Selected Papers
EditoresIsidoro Gitler, Jaime Klapp, Andrei Tchernykh, Moises Torres
EditorialSpringer Verlag
Páginas11-23
Número de páginas13
ISBN (versión impresa)9783030104474
DOI
EstadoPublicada - 2019
Evento9th International Conference on Supercomputing, ISUM 2018 - Mérida, México
Duración: 5 mar. 20189 mar. 2018

Serie de la publicación

NombreCommunications in Computer and Information Science
Volumen948
ISSN (versión impresa)1865-0929

Conferencia

Conferencia9th International Conference on Supercomputing, ISUM 2018
País/TerritorioMéxico
CiudadMérida
Período5/03/189/03/18

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