Evolving embedded fuzzy controllers

The interest in research and implementations of type-2 fuzzy controllers (T2FCs) is increasing. It has been demonstrated that these controllers provide more advantages in handling uncertainties than type-1 FCs (T1FCs). This characteristic is very appealing because real-world problems are full of inaccurate information from diverse sources. Nowadays, it is no problem to implement an intelligent controller (IC) for microcomputers since they offer powerful operating systems, high-level languages, microprocessors with several cores, and co-processing capacities on graphic processing units (GPUs), which are interesting characteristics for the implementation of fast type-2 ICs (T2ICs). However, the above benefits are not directly available for the design of embedded ICs for consumer electronics that need to be implemented in devices such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGAs), etc. Fortunately, for T1FCs there are platforms that generate code in VHSIC hardware description language (VHDL; VHSIC: very high speed integrated circuit), C++, and Java. This is not true for the design of T2ICs, since there are no specialized tools to develop the inference system as well as to optimize it. The aim of this chapter is to present different ways of achieving high-performance computing for evolving T1 and T2 ICs embedded into FPGAs. Therefore, we provide a compiled introduction to T1 and T2 FCs, with emphasis on the well-known bottle neck of the interval T2FC (IT2FC), and software and hardware proposals to minimize its effect regarding computational cost. An overview of learning systems and hosting technology for their implementation is given. We explain different ways to achieve such implementations: at the circuit level using a hardware description language, using a multiprocessor system and a high-level language, and combining both methods. We explain how to use the IT2FC developed in VHDL as a standalone system, and as a coprocessor for the FPGA Fusion of Actel, Spartan 6, and Virtex 5. We present the methodology and two new proposals to achieve evolution of the IT2FC for FPGA, one for the static region of the FPGA, and the other one for the reconfigurable region using the dynamic partial reconfiguration methodology.