TY - GEN
T1 - An optimized SVPWM scheme for a thirteen-level inverter
AU - Flores-Acoltzi, Onesimo
AU - Araujo-Vargas, Ismael
AU - Mondragón-Escamilla, Nancy
AU - Ponce-Flores, Mario
AU - Valencia-Figueroa, Fermín
N1 - Publisher Copyright:
© 2016, Institution of Engineering and Technology. All rights reserved.
PY - 2016
Y1 - 2016
N2 - This paper presents an improved Space Vector PWM (SVPWM) strategy for an unusual thirteen-level inverter that has symmetric space vectors with few redundant switching states. In comparison to conventional topologies of multi-level inverters that utilise complex cascade H-bridges with isolated DC sources or Neutral Point Clamped (NPC) circuits, the multi-level inverter presented in this work uses a single DC supply and a three-phase transformer coupling. The improved SVPWM scheme facilitates the location of the reference voltage vector in the space vector plane and the determination of the semiconductor devices switching. The principle of operation of the thirteen-level inverter is analysed, showing how an optimized SVPWM technique was implemented on a low-cost FPGA to operate a 2kW, 13-level inverter prototype, and experimental results are shown to validate the operation of the converter under steady-state and dynamic conditions.
AB - This paper presents an improved Space Vector PWM (SVPWM) strategy for an unusual thirteen-level inverter that has symmetric space vectors with few redundant switching states. In comparison to conventional topologies of multi-level inverters that utilise complex cascade H-bridges with isolated DC sources or Neutral Point Clamped (NPC) circuits, the multi-level inverter presented in this work uses a single DC supply and a three-phase transformer coupling. The improved SVPWM scheme facilitates the location of the reference voltage vector in the space vector plane and the determination of the semiconductor devices switching. The principle of operation of the thirteen-level inverter is analysed, showing how an optimized SVPWM technique was implemented on a low-cost FPGA to operate a 2kW, 13-level inverter prototype, and experimental results are shown to validate the operation of the converter under steady-state and dynamic conditions.
KW - FPGA
KW - Space vector PWM (SVPWM)
KW - Thirteen-level inverter
KW - Three-phase transformer
UR - http://www.scopus.com/inward/record.url?scp=85009083802&partnerID=8YFLogxK
U2 - 10.1049/cp.2016.0189
DO - 10.1049/cp.2016.0189
M3 - Contribución a la conferencia
AN - SCOPUS:85009083802
SN - 9781785611889
T3 - IET Conference Publications
BT - IET Conference Publications
PB - Institution of Engineering and Technology
T2 - 8th IET International Conference on Power Electronics, Machines and Drives, PEMD 2016
Y2 - 19 April 2016 through 21 April 2016
ER -