A low-cost and highly compact FPGA-based encryption/decryption architecture for AES algorithm

Nowadays, the design of ultra-compact area advanced encryption standard (AES) architectures is highly demanded by the electronics industry since many of these architectures are embedded in portable devices, such as smart phones, tablets, etc., in which the area is critically limited. Until now, many approaches have been proposed to create high-processing and compact architectures. However, the area consumption is still a factor to be improved. In this paper, a highly compact encryption/decryption architecture, which is implemented in a low-cost FPGA, to efficiently simulate the AES algorithm, is proposed. Specifically, an optimized Galois Field Multiplier, which is the most demanding operation in terms of area consumption and processing speed, involved in Mix-Columns and Inverse Mix-Columns transformations, is presented. Therefore, the optimization of the proposed GF (28) multiplier by two has allowed to us create an ultra-compact Mix-Columns circuit since this circuit involves large number of multiplications. In addition, the design involves a routing circuit which allowed the proposed architecture to perform encryption or decryption by using common modules. The results demonstrate that the proposed digital circuit expends fewer LUTs and fewer registers when compared with the most compact encryption/decryption architectures reported to date.