TY - JOUR
T1 - 3D substrate modeling; From a first order electrical analysis, towards some possible signal fluctuations consideration, for radio frequency circuits
AU - Gontrand, Christian
AU - Sun, Fengyuan
AU - Ricardo Cardenas-Valdez, José
AU - Ma, Yue
AU - Plossu, Carole
AU - Calmon, Francis
AU - Cruz Nuñez-Perez, José
AU - Verdier, Jacques
N1 - Funding Information:
This work is supported by INFIERI (Intelligent Fast Interconnected and Efficient Devices for Frontier Exploitation in Research and Industry Program), the U.S. Department of Energy and National Science Foundation, the Italian Instituto Nazionale di Fisica Nucleare, the EU Community FP7–2012-ITN Contract 317446, Two of us (Fengyuan Sun and Yue Ma) thank the China Scholarship Council (CSC).
PY - 2014/8
Y1 - 2014/8
N2 - 3D Si integration seems a right way to go and compete with Moores law (more than Moore versus more Moore). However, it is still a long way to go. In 2010, the question was: why 3D? Today, the questions are: when 3D? and how 3D? The 3D chip stacking is considered known to overcome conventional 2D-IC issues, using in-depth contacts or some trough silicon via for signal transmission. First of all, from any source, we calculate the staggered impedance. For this, our approach is, at least, twofold: a compact Green kernel, or transmission line model, over or into a multi-layered substrate, is derived by solving Poissons equation analytically. The discrete cosine transform and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in ICs can be analyzed. We implement our algorithm in MATLAB. Thus, it permits to extract impedances between any two embedded contacts, real or virtual; this is original, up to our knowledge. We investigate our models on both analytical and numerical methods, like finite elements-based simulations. This extended model enables one to extract substrate impedance and parasitic elements between any two points embedded into the substrate. They are fully compatible with SPICE-like solvers and should allow an investigation in depth of the impact of buried contacts on circuit performance. This work should be an opening for an in depth study on the transfer impedance method concept applied to tridimensional calculations of noise,
AB - 3D Si integration seems a right way to go and compete with Moores law (more than Moore versus more Moore). However, it is still a long way to go. In 2010, the question was: why 3D? Today, the questions are: when 3D? and how 3D? The 3D chip stacking is considered known to overcome conventional 2D-IC issues, using in-depth contacts or some trough silicon via for signal transmission. First of all, from any source, we calculate the staggered impedance. For this, our approach is, at least, twofold: a compact Green kernel, or transmission line model, over or into a multi-layered substrate, is derived by solving Poissons equation analytically. The discrete cosine transform and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in ICs can be analyzed. We implement our algorithm in MATLAB. Thus, it permits to extract impedances between any two embedded contacts, real or virtual; this is original, up to our knowledge. We investigate our models on both analytical and numerical methods, like finite elements-based simulations. This extended model enables one to extract substrate impedance and parasitic elements between any two points embedded into the substrate. They are fully compatible with SPICE-like solvers and should allow an investigation in depth of the impact of buried contacts on circuit performance. This work should be an opening for an in depth study on the transfer impedance method concept applied to tridimensional calculations of noise,
KW - 3D circuits
KW - Green kernels
KW - Modeling
KW - Noise
KW - RF
KW - Substrate impedance
UR - http://www.scopus.com/inward/record.url?scp=84902489078&partnerID=8YFLogxK
U2 - 10.1016/j.mejo.2014.04.037
DO - 10.1016/j.mejo.2014.04.037
M3 - Artículo
SN - 0026-2692
VL - 45
SP - 1061
EP - 1068
JO - Microelectronics Journal
JF - Microelectronics Journal
IS - 8
ER -