Spike-based compact digital neuromorphic architecture for efficient implementation of high order FIR filters

Finite impulse response (FIR) filters have been widely used in many digital signal processing applications because of their interesting properties such as phase linearity, bounded-input-bounded-output (BIBO) stability and easy implementation. However, the implementation of high order filters requires many multipliers. Several authors have proposed new methods such as multiple constant multiplication (MCM), distributed arithmetic (DA) and signed-powers-of-two (SPT) to avoid the use of multipliers by using the minimum number of registers. Nevertheless, the implementation of these strategies generates critical paths that limit their performance. In this work, we propose a compact hardware architecture to compute FIR filters at high processing speeds using new parallel neural multipliers. The scalability of the system enables the construction of many neural multiplier units for higher order FIR filters. To validate the proposal, the hardware architecture was implemented on the Kintex-7 field programmable gate array (FPGA) development kit. The results demonstrate that this new approach can be interfaced with the conventional binary systems to improve advanced signal processing applications such as high quality media contents, wireless communication and biomedical systems.