Abstract
The results of a study of a family of parallel symbolic architectures executing several parallel applications are presented. The class of architectures being simulated is characterized by a shared memory structure, by a hierarchical interconnect, and by clustered processors. Speedup measurements were obtained from six different application kernels. Measurements were also performed to assess the degradation of speedup as a function of the interconnection delays, and to study the effect of different scheduling algorithms. The results presented support the claim that the proposed architecture would be a powerful parallel symbolic computation system. The paper discusses processor starvation, fine grain parallelism, unever loads, foreign reference, schedule and indeterminate computation with respect to the applications chosen.
Original language | English |
---|---|
Pages (from-to) | 183-214 |
Number of pages | 32 |
Journal | International Journal of Parallel Programming |
Volume | 16 |
Issue number | 3 |
DOIs | |
State | Published - Jun 1987 |
Externally published | Yes |
Keywords
- Symbolic applications
- architecture
- parallel
- performance