LMS algorithm for programming an analogue memory cell

Jesús De La Cruz-Alejo, L. Noé Oliva-Moreno

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

This article presents the optimal performance of a nonvolatile analogue memory cell fabricated in 1.2 μm CMOS process, which is programmed using a LMS (least mean square) algorithm to implement an adaptive FIR filter used to identify an unknown signal. The memory cell is programmed to store and update the weight in the filter as charge in the floating gate of a pMOS transistor (FGMOS). Programming is linear using a pulse density modulation scheme by means of tunnelling and hot injection electrons. The behavior of the memory is included and programming method is developed. The LMS algorithm performed very well, and does not require the signal to be piecewise stationary, and requires no manual operation other than selection of the step-size of the adaptive parameter.

Original languageEnglish
Pages (from-to)863-879
Number of pages17
JournalInternational Journal of Electronics
Volume100
Issue number6
DOIs
StatePublished - 1 Jun 2013

Keywords

  • CMOS-transistor
  • LMS-algorithm
  • adaptive
  • filter
  • floating-gate
  • injection
  • memory
  • tunnelling, update
  • weight

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