High precision programmable adaptive digital frequency multiplier

M. A. Partida; A. de Luca; J. G. Delgado-Frias; J. Goddard; R. U. Parrazales

High precision programmable adaptive digital frequency multiplier

M. A. Partida, A. de Luca, J. G. Delgado-Frias, J. Goddard, R. U. Parrazales

Centro de Investigación en Computación (CIC)

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

This paper presents and justifies the use of an architecture which increases the precision in the output pulse of an adaptive frequency multiplier. This is done without using a correction circuit, a component which was necessary in previous work in the area.

Original language	English
Pages	385-388
Number of pages	4
State	Published - 1995
Event	Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Rio de Janeiro, Braz Duration: 13 Aug 1995 → 16 Aug 1995

Conference

Conference	Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
City	Rio de Janeiro, Braz
Period	13/08/95 → 16/08/95

Cite this

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title = "High precision programmable adaptive digital frequency multiplier",

abstract = "This paper presents and justifies the use of an architecture which increases the precision in the output pulse of an adaptive frequency multiplier. This is done without using a correction circuit, a component which was necessary in previous work in the area.",

author = "Partida, {M. A.} and {de Luca}, A. and Delgado-Frias, {J. G.} and J. Goddard and Parrazales, {R. U.}",

year = "1995",

language = "Ingl{\'e}s",

pages = "385--388",

note = "Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2) ; Conference date: 13-08-1995 Through 16-08-1995",

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AU - Partida, M. A.

AU - de Luca, A.

AU - Delgado-Frias, J. G.

AU - Goddard, J.

AU - Parrazales, R. U.

PY - 1995

Y1 - 1995

N2 - This paper presents and justifies the use of an architecture which increases the precision in the output pulse of an adaptive frequency multiplier. This is done without using a correction circuit, a component which was necessary in previous work in the area.

AB - This paper presents and justifies the use of an architecture which increases the precision in the output pulse of an adaptive frequency multiplier. This is done without using a correction circuit, a component which was necessary in previous work in the area.

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M3 - Artículo

AN - SCOPUS:0029459208

SP - 385

EP - 388

T2 - Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems. Part 1 (of 2)

Y2 - 13 August 1995 through 16 August 1995

ER -

High precision programmable adaptive digital frequency multiplier

Abstract

Conference

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