HF noise behavior and small signal modeling of strained Si HFETs

High Frequency (HF) noise performance of strained Si HFETs is studied. Noise parameter of devices with buried strained pure Si channel fabricated on several strain relieved virtual substrate (SRB) are presented. The influence of such SRB on device noise performance is estimated by a proper noise de-embedding technique. The impact of device gate length on noise parameters is presented. High frequency noise properties measured in the 2.5-12 GHz frequency range are simulated using Pospieszalski's and Van Der Ziel's noise models by means of the small signal equivalent circuit linked to parasitic pads, lines and substrate losses. Good agreement obtained between experimental data and modeling enables the investigation of the main contributions to n-HFET noise properties. Detrimental effects that negatively impact the microwave noise behavior are elucidated and some alternatives to overwhelm them are proposed. Noise modeling is useful to predict further improvements of RF and noise performance when shrinking the gate length below 100 nm.