TY - GEN
T1 - FPGA-Based Emulation of Sequential Least Squares for Coefficient Extraction of RF Power Amplifiers
AU - Perez, Jose Cruz Nunez
AU - Chavez, Edgar Allende
AU - Valdez, Jose Ricardo Cardenas
AU - Rodriguez, Aldo Bonilla
AU - Leon, Gamaliel Entrambasaguas
AU - Andrade, Rodrigo Yaoctzin Serrato
AU - Aguilar, Jose Alejandro Galaviz
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/11
Y1 - 2018/11
N2 - The present paper shows the full design and implementation in VHDL code of the sequential least squares algorithm to obtain the coefficients of the memory polynomial model. This model was selected to perform the behavioral modeling of power amplifiers for RF. Two main parts make up the design: a memory polynomial model with unit coefficients block and a sequential least squares calculation block. The design allows the extraction of the coefficients by providing only an input and an output of the power amplifier and makes the model more accurate with each iteration, it works with complex values which makes it possible modeling the amplitude-amplitude and amplitude-phase curves in a single model. The implementation was made through the Stratix IV DSP-FPGA development board and tested using 65,536 samples from a power amplifier NXP 10W measured at 2 GHz, achieving, an NMSE of-19.6884 dB.
AB - The present paper shows the full design and implementation in VHDL code of the sequential least squares algorithm to obtain the coefficients of the memory polynomial model. This model was selected to perform the behavioral modeling of power amplifiers for RF. Two main parts make up the design: a memory polynomial model with unit coefficients block and a sequential least squares calculation block. The design allows the extraction of the coefficients by providing only an input and an output of the power amplifier and makes the model more accurate with each iteration, it works with complex values which makes it possible modeling the amplitude-amplitude and amplitude-phase curves in a single model. The implementation was made through the Stratix IV DSP-FPGA development board and tested using 65,536 samples from a power amplifier NXP 10W measured at 2 GHz, achieving, an NMSE of-19.6884 dB.
KW - FPGA
KW - Memory Polynomial Model
KW - Power Amplifier
KW - SLS
KW - VHDL
UR - http://www.scopus.com/inward/record.url?scp=85068858210&partnerID=8YFLogxK
U2 - 10.1109/ICMEAE.2018.00039
DO - 10.1109/ICMEAE.2018.00039
M3 - Contribución a la conferencia
AN - SCOPUS:85068858210
T3 - Proceedings - 2018 International Conference on Mechatronics, Electronics and Automotive Engineering, ICMEAE 2018
SP - 171
EP - 176
BT - Proceedings - 2018 International Conference on Mechatronics, Electronics and Automotive Engineering, ICMEAE 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Conference on Mechatronics, Electronics and Automotive Engineering, ICMEAE 2018
Y2 - 27 November 2018 through 30 November 2018
ER -