Electrical stress in CdS thin film transistors using HfO<inf>2</inf> gate dielectric

R. García, I. Mejia, J. E. Molinar-Solis, A. L. Salas-Villasenor, A. Morales, B. García, M. A. Quevedo-Lopez, M. Alemán

Research output: Contribution to journalArticleResearchpeer-review

5 Citations (Scopus)

Abstract

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I on/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve. © 2013 AIP Publishing LLC.
Original languageAmerican English
JournalApplied Physics Letters
DOIs
StatePublished - 20 May 2013

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Gate dielectrics
Thin film transistors
Threshold voltage
Charge trapping
transistors
threshold voltage
thin films
Semiconductor materials
trapping
shift
Electric potential
slopes
output
electric potential
curves

Cite this

García, R., Mejia, I., Molinar-Solis, J. E., Salas-Villasenor, A. L., Morales, A., García, B., ... Alemán, M. (2013). Electrical stress in CdS thin film transistors using HfO<inf>2</inf> gate dielectric. Applied Physics Letters. https://doi.org/10.1063/1.4807720
García, R. ; Mejia, I. ; Molinar-Solis, J. E. ; Salas-Villasenor, A. L. ; Morales, A. ; García, B. ; Quevedo-Lopez, M. A. ; Alemán, M. / Electrical stress in CdS thin film transistors using HfO<inf>2</inf> gate dielectric. In: Applied Physics Letters. 2013.
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abstract = "During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I on/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve. {\circledC} 2013 AIP Publishing LLC.",
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García, R, Mejia, I, Molinar-Solis, JE, Salas-Villasenor, AL, Morales, A, García, B, Quevedo-Lopez, MA & Alemán, M 2013, 'Electrical stress in CdS thin film transistors using HfO<inf>2</inf> gate dielectric', Applied Physics Letters. https://doi.org/10.1063/1.4807720

Electrical stress in CdS thin film transistors using HfO<inf>2</inf> gate dielectric. / García, R.; Mejia, I.; Molinar-Solis, J. E.; Salas-Villasenor, A. L.; Morales, A.; García, B.; Quevedo-Lopez, M. A.; Alemán, M.

In: Applied Physics Letters, 20.05.2013.

Research output: Contribution to journalArticleResearchpeer-review

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T1 - Electrical stress in CdS thin film transistors using HfO2 gate dielectric

AU - García, R.

AU - Mejia, I.

AU - Molinar-Solis, J. E.

AU - Salas-Villasenor, A. L.

AU - Morales, A.

AU - García, B.

AU - Quevedo-Lopez, M. A.

AU - Alemán, M.

PY - 2013/5/20

Y1 - 2013/5/20

N2 - During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I on/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve. © 2013 AIP Publishing LLC.

AB - During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I on/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve. © 2013 AIP Publishing LLC.

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García R, Mejia I, Molinar-Solis JE, Salas-Villasenor AL, Morales A, García B et al. Electrical stress in CdS thin film transistors using HfO<inf>2</inf> gate dielectric. Applied Physics Letters. 2013 May 20. https://doi.org/10.1063/1.4807720