TY - GEN
T1 - Digital architecture for real time processing in vision systems for control of traffic lights
AU - Garcia-Lamont, Jair
AU - Gonzalez-Vidal, Jose L.
AU - Acevedo-Mosqueda, Marco
PY - 2007
Y1 - 2007
N2 - Digital architecture for real time processing in vision systems for control of traffic lights is presented. The main idea of this work is to identify cars on intersections, switching traffic lights in order to reduce traffic jam. The architecture is based on a color image segmentation algorithm that comprises three stages. Stage one is a color space transformation in order to measure the color difference properly, image colors are represented in a modified L* u* v* color space. Stage two consists in a color reduction, where image colors are projected into a small set of prototypes using a self-organizing map (SOM). Stage three realizes color clustering, where simulated annealing (SA) seeks the optimal clusters from SOM prototypes. The proposed hardware architecture is implemented in a Virtex II Pro FPGA and tested; having a processing time inferior to 25ms per 128×128 pixels. The implementation comprises 262,479 equivalent gates.
AB - Digital architecture for real time processing in vision systems for control of traffic lights is presented. The main idea of this work is to identify cars on intersections, switching traffic lights in order to reduce traffic jam. The architecture is based on a color image segmentation algorithm that comprises three stages. Stage one is a color space transformation in order to measure the color difference properly, image colors are represented in a modified L* u* v* color space. Stage two consists in a color reduction, where image colors are projected into a small set of prototypes using a self-organizing map (SOM). Stage three realizes color clustering, where simulated annealing (SA) seeks the optimal clusters from SOM prototypes. The proposed hardware architecture is implemented in a Virtex II Pro FPGA and tested; having a processing time inferior to 25ms per 128×128 pixels. The implementation comprises 262,479 equivalent gates.
KW - Computer vision
KW - FPGA implementation
KW - Image segmentation
KW - Neural-networks
KW - Real-time processing
UR - http://www.scopus.com/inward/record.url?scp=34548220491&partnerID=8YFLogxK
U2 - 10.1117/12.704697
DO - 10.1117/12.704697
M3 - Contribución a la conferencia
AN - SCOPUS:34548220491
SN - 0819466093
SN - 9780819466099
T3 - Proceedings of SPIE - The International Society for Optical Engineering
BT - Proceedings of SPIE-IS and T Electronic Imaging - Real-Time Image Processing 2007
T2 - Real-Time Image Processing 2007
Y2 - 29 January 2007 through 30 January 2007
ER -