Design of ΣΔ modulators using FGMOS transistors

Dora Inés Reyes Chávez, Jesús De La Cruz Alejo, Juan Carlos Sánchez García

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents the design of a second order continuous time low power and low voltage oversampling ΣΔ Modulator. This shows inside a comparator and an integrator with FGMOS techniques to facilitate the design and improve its characteristic behavior. The FGMOS transistor is simultaneously used in order to simplify the topology, accurately compensate for gain losses in the integrator and several nonidealities in the comparator; increase the dynamic range; reduce distortion; shift signal levels according to the specific requirements of individual devices; implement an easy common-mode sensing and feedback strategy; and tune the loop filter and reset the comparator. The ΣΔ Modulator operates with 2 kHz of band with 2V and consumes just 7.5 μW of power. The simulation results are according to theoretical analysis.

Original languageEnglish
Title of host publicationCCE 2011 - 2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control, Program and Abstract Book
DOIs
StatePublished - 2011
Event2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2011 - Merida, Yucatan, Mexico
Duration: 26 Oct 201128 Oct 2011

Publication series

NameCCE 2011 - 2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control, Program and Abstract Book

Conference

Conference2011 8th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2011
Country/TerritoryMexico
CityMerida, Yucatan
Period26/10/1128/10/11

Keywords

  • Floating-Gate MOS (FGMOS)
  • ΣΔ Modulators

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