Compressive sensing architecture for gray scale images

This paper proposes a compressive sensing architecture for 128 × 128 pixels gray scale images. The proposed architecture is implemented in an FPGA platform. Due to speed and area advantages, the random numbers block generator is implemented using Linear Feedback Shift Register (LFSR) technique. The resulting random matrix is stored in a Random Access Memory (RAM) block. In addition, a second RAM is employed to store the sampled image. We also implement an Universal Asynchronous Receiver Transmitter (UART) to receive and transmit data. Besides the previous blocks, we design an Arithmetic/Logic Unit (ALU), which performs the operations in compressive sensing settings. In this way, a Unit Control (UC) based on a Mealy type state machine directs operations in our architecture. The purpose of the UC is threefold. First, the UC uses the UART to receive the sample image and store it in the corresponding RAM block. Second, the UC directs the matrix multiplication operation to the ALU and obtains the compressed image. Finally, the UART transmits the compressed image to a base station. The main characteristics of our architecture are the following: the maximum frequency of operation is 30 MHz, the power consumption is 37 mW, and the average time processing is 4.5 ms.