Compresión de la señal de radar usando FPGA

We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of side-lobes. The proposed architecture exploits the parallel computing resources of FPGA devices to achieve better computation speed. Experimental investigations have shown that the best results for pulse compression performance have been obtained using atomic functions, improving the performance of the radar system in the presence of noise, obtaining small degradation in range resolution. Implementation of the signal processing in the radar system for real time mode is discussed here and the effectiveness of the proposed hardware architecture has been justified.