TY - JOUR
T1 - Codesign for Generation of Large Random Sequences on Zynq FPGA
AU - Hernandez-Morales, Brenda Mariana
AU - Diaz-Santiago, Sandra
AU - Mancillas-Lopez, Cuauhtemoc
N1 - Publisher Copyright:
© 2009-2012 IEEE.
PY - 2023/6/1
Y1 - 2023/6/1
N2 - This work presents two codesign implementations of a true random number generation mechanism. Physical components provided by the programmable logic of FPGA are used for true random seed generation. The seed conditioning and generation of the large sequences were implemented using the block cipher Advanced Encryption Standard (AES) implemented on the Cortex-A9 processor (embedded in the Zynq FPGA) or specific AESNI instructions in modern processors. Our implementations use less than 10% of the available resources on the target FPGAs and pass all the National Institute of Standards and Technology (NIST) tests for random generators.
AB - This work presents two codesign implementations of a true random number generation mechanism. Physical components provided by the programmable logic of FPGA are used for true random seed generation. The seed conditioning and generation of the large sequences were implemented using the block cipher Advanced Encryption Standard (AES) implemented on the Cortex-A9 processor (embedded in the Zynq FPGA) or specific AESNI instructions in modern processors. Our implementations use less than 10% of the available resources on the target FPGAs and pass all the National Institute of Standards and Technology (NIST) tests for random generators.
KW - Cryptography
KW - pseudorandomness
KW - transition effect ring oscillator (TERO)
KW - true random number generator (TRNG)
UR - http://www.scopus.com/inward/record.url?scp=85133763456&partnerID=8YFLogxK
U2 - 10.1109/LES.2022.3184653
DO - 10.1109/LES.2022.3184653
M3 - Artículo
AN - SCOPUS:85133763456
SN - 1943-0663
VL - 15
SP - 77
EP - 80
JO - IEEE Embedded Systems Letters
JF - IEEE Embedded Systems Letters
IS - 2
ER -