An ultra-compact and high-speed FFT-based large-integer multiplier for fully homomorphic encryption using a dual spike-based arithmetic circuit over GF(p)

Luis Garcia, Eduardo Vazquez, Gabriel Sanchez, Juan Gerardo Avalos, Giovanny Sanchez

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

During last years, fully homomorphic encryption (FHE) has attracted great interest since enables computation on encrypted data and thus can be considered as a potential solution in advanced applications, such as privacy-preserving cloud computing, genomics, electronic voting and bio-metric authentication. Nowadays, software simulations of the FHE schemes on general purpose computers are extremely slow. Therefore, the development of specific hardware architectures open up new horizons in efficient simulation of FHE schemes. Until date, the implementation of FHE schemes in embedded devices remain impractical due to very high processing time and area consumption required to process very large-integer numbers. Specifically, the development of efficient very large-integer finite-field adder and multiplier potentially allows the throughput and area consumption to be improved since these circuits are the most used components in the computation of FHE schemes. This work presents, for the first time, the development of a compact and highly dual finite-field circuit based on spiking neural P systems (SN P), dendritic growth, dendritic pruning, communication on request and structural plasticity. Specifically, this circuit performs either the finite-field addition or multiplication of two variable integers by only reconnecting their synapses dynamically. Hence, the proposed circuit performs both operations employing the same neural network. In this way, we achieve a significant improvement in terms of area consumption and throughput. Since the computation of FHE schemes requires the multiplication of very large-integer numbers, we use the proposed dual finite-field circuit as the basic processing unit to create a very large-integer multiplier based on fast Fourier transform (FFT). Specifically, the creation of the proposed very large-integer multiplier has allowed us to accelerate the key generation and encryption processes involved in the computation of FHE algorithm. This multiplier was implemented in scalable compact neuromorphic architecture, which mimic the dynamic dendritic phenomena, such as dendritic growth and dendritic pruning. To achieve this, we propose a dynamic multiplexing mechanism based on simple multiplexers and an optimized control unit. This have allowed us to significantly improve the area consumption compared with previously reported solution.

Original languageEnglish
Pages (from-to)54-66
Number of pages13
JournalNeurocomputing
Volume507
DOIs
StatePublished - 1 Oct 2022

Keywords

  • Astrocyte-like control
  • Dendritic delay
  • Dendritic delays
  • Dendritic feedback
  • Dendritic growth
  • Dendritic pruning
  • FPGA
  • Fast fourier transform
  • Finite-field adder
  • Finite-field adder multiplier
  • Spiking neural P system

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