An architecture of quantum CPU

Víctor H. Téllez; Antonio Campero; Cristina Iuga; Gonzalo Duchen

An architecture of quantum CPU

Víctor H. Téllez, Antonio Campero, Cristina Iuga, Gonzalo Duchen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We present a quantum CPU (central processing unit) which is based on the quantum gate set. Using the Von Neuman model, the quantum CPU has development on a classical Digital Signal Processor (DSP TI6711). The DSP simulated different gates, as the Feynman gate, and the set of the different gates make possible the quantum CPU. Generically, hardware of the quantum CPU are modeled in terms of quantum spins (qubits) that evolve in time according to the time-dependent Schrodinger equation (TDSE). Furthermore, we will try quantum error-correcting code to fight de coherence and operational errors.

Original language	English
Title of host publication	2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings
Pages	205-208
Number of pages	4
State	Published - 2007
Externally published	Yes
Event	2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007 - Santa Clara, CA, United States Duration: 20 May 2007 → 24 May 2007

Publication series

Name	2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings
Volume	3

Conference

Conference	2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007
Country/Territory	United States
City	Santa Clara, CA
Period	20/05/07 → 24/05/07

Keywords

Parallel processing
Pipeline processing
Processing unit simulator
Short's factorization

Cite this

@inproceedings{089db21353e443a9a9faed361d3ce05b,

title = "An architecture of quantum CPU",

abstract = "We present a quantum CPU (central processing unit) which is based on the quantum gate set. Using the Von Neuman model, the quantum CPU has development on a classical Digital Signal Processor (DSP TI6711). The DSP simulated different gates, as the Feynman gate, and the set of the different gates make possible the quantum CPU. Generically, hardware of the quantum CPU are modeled in terms of quantum spins (qubits) that evolve in time according to the time-dependent Schrodinger equation (TDSE). Furthermore, we will try quantum error-correcting code to fight de coherence and operational errors.",

keywords = "Parallel processing, Pipeline processing, Processing unit simulator, Short's factorization",

author = "T{\'e}llez, {V{\'i}ctor H.} and Antonio Campero and Cristina Iuga and Gonzalo Duchen",

year = "2007",

language = "Ingl{\'e}s",

isbn = "1420063421",

series = "2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings",

pages = "205--208",

booktitle = "2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings",

note = "2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007 ; Conference date: 20-05-2007 Through 24-05-2007",

}

Téllez, VH, Campero, A, Iuga, C & Duchen, G 2007, An architecture of quantum CPU. in 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings. 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings, vol. 3, pp. 205-208, 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Santa Clara, CA, United States, 20/05/07.

An architecture of quantum CPU. / Téllez, Víctor H.; Campero, Antonio; Iuga, Cristina et al.
2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings. 2007. p. 205-208 (2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An architecture of quantum CPU

AU - Téllez, Víctor H.

AU - Campero, Antonio

AU - Iuga, Cristina

AU - Duchen, Gonzalo

PY - 2007

Y1 - 2007

N2 - We present a quantum CPU (central processing unit) which is based on the quantum gate set. Using the Von Neuman model, the quantum CPU has development on a classical Digital Signal Processor (DSP TI6711). The DSP simulated different gates, as the Feynman gate, and the set of the different gates make possible the quantum CPU. Generically, hardware of the quantum CPU are modeled in terms of quantum spins (qubits) that evolve in time according to the time-dependent Schrodinger equation (TDSE). Furthermore, we will try quantum error-correcting code to fight de coherence and operational errors.

AB - We present a quantum CPU (central processing unit) which is based on the quantum gate set. Using the Von Neuman model, the quantum CPU has development on a classical Digital Signal Processor (DSP TI6711). The DSP simulated different gates, as the Feynman gate, and the set of the different gates make possible the quantum CPU. Generically, hardware of the quantum CPU are modeled in terms of quantum spins (qubits) that evolve in time according to the time-dependent Schrodinger equation (TDSE). Furthermore, we will try quantum error-correcting code to fight de coherence and operational errors.

KW - Parallel processing

KW - Pipeline processing

KW - Processing unit simulator

KW - Short's factorization

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M3 - Contribución a la conferencia

AN - SCOPUS:34547968925

SN - 1420063421

SN - 9781420063424

SN - 1420061844

SN - 9781420061840

T3 - 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings

SP - 205

EP - 208

BT - 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings

T2 - 2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007

Y2 - 20 May 2007 through 24 May 2007

ER -

An architecture of quantum CPU

Abstract

Publication series

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Keywords

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Cite this