TY - JOUR
T1 - A 90 μm × 64 μm 225 μw class-AB CMOS differential flipped voltage follower with output driving capability up to 100 pF
AU - Muñiz-Montero, C.
AU - Sánchez-Gaspariano, L. A.
AU - Camacho-Escoto, J. J.
AU - Villa-Vargas, L. A.
AU - Molina-Lozano, H.
AU - Molinar-Solís, J. E.
N1 - Funding Information:
The authors thank the National Council of Science and Technology (CONACyT) of Mexico for the financial support through the project 181201-Y , and the Program for Faculty Improvement (PROMEP) of Mexico who partially supported this work through the project F-PROMEP-39/Rev-03 .
PY - 2013/10
Y1 - 2013/10
N2 - A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5μm CMOS technology and the Pelgrom's mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology.
AB - A compact differential flipped voltage follower (DFVF) with low power consumption, capable to deliver currents several orders of magnitude larger than its quiescent current and with large capacitive loads is presented. In the proposed circuit, a current comparator activates an auxiliary transistor whenever is required to hand over additional current and reach class-AB operation. Furthermore, Miller compensation is performed, by taking advantage of the large impedance node of the comparator it is possible to reduce forty times the compensation capacitor compared to other topologies under the same conditions. The proposed architecture is validated by post-layout simulations using the parameters of an ON SEMI, double-poly, three metal layers, 0.5μm CMOS technology and the Pelgrom's mismatch model. A Winner-Takes-All circuit, a median filter and a current conveyor are presented as examples of application of the proposed topology.
KW - Analog CMOS
KW - Current comparators
KW - Current conveyors
KW - Flipped voltage followers
KW - Winner-Takes-All circuits
UR - http://www.scopus.com/inward/record.url?scp=84886096965&partnerID=8YFLogxK
U2 - 10.1016/j.mejo.2013.03.002
DO - 10.1016/j.mejo.2013.03.002
M3 - Artículo
AN - SCOPUS:84886096965
SN - 0026-2692
VL - 44
SP - 930
EP - 940
JO - Microelectronics Journal
JF - Microelectronics Journal
IS - 10
ER -