Electrical stress in CdS thin film transistors using HfO2 gate dielectric

R. García; I. Mejia; J. E. Molinar-Solis; A. L. Salas-Villasenor; A. Morales; B. García; M. A. Quevedo-Lopez; M. Alemán

doi:10.1063/1.4807720

Electrical stress in CdS thin film transistors using HfO₂ gate dielectric

R. García, I. Mejia, J. E. Molinar-Solis, A. L. Salas-Villasenor, A. Morales, B. García, M. A. Quevedo-Lopez, M. Alemán

Centro de Investigación en Computación (CIC)

Producción científica: Contribución a una revista › Artículo › revisión exhaustiva

8 Citas (Scopus)

Resumen

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO₂ as gate dielectric is analyzed. Threshold voltage, I _on/I_off ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.

Idioma original	Inglés
Número de artículo	203505
Publicación	Applied Physics Letters
Volumen	102
N.º	20
DOI	https://doi.org/10.1063/1.4807720
Estado	Publicada - 20 may. 2013

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abstract = "During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I on/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.",

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T1 - Electrical stress in CdS thin film transistors using HfO2 gate dielectric

AU - García, R.

AU - Mejia, I.

AU - Molinar-Solis, J. E.

AU - Salas-Villasenor, A. L.

AU - Morales, A.

AU - García, B.

AU - Quevedo-Lopez, M. A.

AU - Alemán, M.

PY - 2013/5/20

Y1 - 2013/5/20

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AB - During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I on/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.

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