TY - GEN
T1 - A fast implementation of multiplicative inversion over GF(2 m)
AU - Rodríguez-Henríquez, Francisco
AU - Saqib, Nazar A.
AU - Cruz-Cortés, Nareli
PY - 2005
Y1 - 2005
N2 - In this paper, an efficient architecture for multiplicative inversion in GF(2 m) using addition chains is presented. The approach followed was based on the Itoh-Tsujii algorithm targeting a fast implementation on reconfigurable hardware devices. We give the design details of the proposed architecture whose main building blocks are a field multi-squarer block, a field polynomial multiplier and a BRAM two-ports memory. Our design is able to compute multiplicative inversion in GF(2 193) in about 1.33μS using only 27 clock cycles.
AB - In this paper, an efficient architecture for multiplicative inversion in GF(2 m) using addition chains is presented. The approach followed was based on the Itoh-Tsujii algorithm targeting a fast implementation on reconfigurable hardware devices. We give the design details of the proposed architecture whose main building blocks are a field multi-squarer block, a field polynomial multiplier and a BRAM two-ports memory. Our design is able to compute multiplicative inversion in GF(2 193) in about 1.33μS using only 27 clock cycles.
UR - http://www.scopus.com/inward/record.url?scp=24744433086&partnerID=8YFLogxK
M3 - Contribución a la conferencia
AN - SCOPUS:24744433086
SN - 0769523153
SN - 9780769523156
T3 - International Conference on Information Technology: Coding and Computing, ITCC
SP - 574
EP - 579
BT - Proceedings ITCC 2005 - International Conference on Information Technology
A2 - Selvaraj, H.
A2 - Srimani, P.K.
T2 - ITCC 2005 - International Conference on Information Technology: Coding and Computing
Y2 - 4 April 2005 through 6 April 2005
ER -