A digital real time image demosaicking implementation for high definition video cameras

Jair Garcia-Lamont; Miguel Aleman-Arce; Julio Waissman-Vilanova

doi:10.1109/CERMA.2008.78

A digital real time image demosaicking implementation for high definition video cameras

Jair Garcia-Lamont, Miguel Aleman-Arce, Julio Waissman-Vilanova

Centro de Investigación en Computación (CIC)

Producción científica: Contribución a una conferencia › Artículo › revisión exhaustiva

6 Citas (Scopus)

Resumen

This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.

Idioma original	Inglés
Páginas	565-569
Número de páginas	5
DOI	https://doi.org/10.1109/CERMA.2008.78
Estado	Publicada - 2008
Evento	Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008 - Cuernavaca, Morelos, México Duración: 30 sep. 2008 → 3 oct. 2008

Conferencia

Conferencia	Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008
País/Territorio	México
Ciudad	Cuernavaca, Morelos
Período	30/09/08 → 3/10/08

Acceder al documento

10.1109/CERMA.2008.78

Otros archivos y enlaces

Enlace a la publicación en Scopus

Citar esto

@conference{54b4b63f3ec54f75aadc41c921439a73,

title = "A digital real time image demosaicking implementation for high definition video cameras",

abstract = "This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.",

author = "Jair Garcia-Lamont and Miguel Aleman-Arce and Julio Waissman-Vilanova",

year = "2008",

doi = "10.1109/CERMA.2008.78",

language = "Ingl{\'e}s",

pages = "565--569",

note = "Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008 ; Conference date: 30-09-2008 Through 03-10-2008",

}

Garcia-Lamont, J, Aleman-Arce, M & Waissman-Vilanova, J 2008, 'A digital real time image demosaicking implementation for high definition video cameras', Papel presentado en Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008, Cuernavaca, Morelos, México, 30/09/08 - 3/10/08 pp. 565-569. https://doi.org/10.1109/CERMA.2008.78

A digital real time image demosaicking implementation for high definition video cameras. / Garcia-Lamont, Jair; Aleman-Arce, Miguel; Waissman-Vilanova, Julio.
2008. 565-569 Papel presentado en Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008, Cuernavaca, Morelos, México.

Producción científica: Contribución a una conferencia › Artículo › revisión exhaustiva

TY - CONF

T1 - A digital real time image demosaicking implementation for high definition video cameras

AU - Garcia-Lamont, Jair

AU - Aleman-Arce, Miguel

AU - Waissman-Vilanova, Julio

PY - 2008

Y1 - 2008

N2 - This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.

AB - This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.

UR - http://www.scopus.com/inward/record.url?scp=67650032735&partnerID=8YFLogxK

U2 - 10.1109/CERMA.2008.78

DO - 10.1109/CERMA.2008.78

M3 - Artículo

SP - 565

EP - 569

T2 - Proceedings - 5th Meeting of the Electronics, Robotics and Automotive Mechanics Conference 2008, CERMA 2008

Y2 - 30 September 2008 through 3 October 2008

ER -

A digital real time image demosaicking implementation for high definition video cameras

Resumen

Conferencia

Acceder al documento

Otros archivos y enlaces

Huella

Citar esto