TY - GEN
T1 - Realizing general MLP networks with minimal FPGA resources
AU - Latino, Carl
AU - Moreno-Armendáriz, Marco A.
AU - Hagan, Martin
PY - 2009
Y1 - 2009
N2 - In recent years, there has been significant interest in implementing neural networks on FPGAs. This paper describes a simple technique for implementing multi-layer neural networks, with arbitrary numbers of neurons and layers, on FPGAs, using minimal resources. The network architecture can be modified simply by loading memory with the architecture parameters and the network weights and biases. The paper also presents an application of the technology, in which a smart position sensor system is implemented with a neural network on a Xilinx Spartan 3E FPGA development system.
AB - In recent years, there has been significant interest in implementing neural networks on FPGAs. This paper describes a simple technique for implementing multi-layer neural networks, with arbitrary numbers of neurons and layers, on FPGAs, using minimal resources. The network architecture can be modified simply by loading memory with the architecture parameters and the network weights and biases. The paper also presents an application of the technology, in which a smart position sensor system is implemented with a neural network on a Xilinx Spartan 3E FPGA development system.
UR - http://www.scopus.com/inward/record.url?scp=70449429572&partnerID=8YFLogxK
U2 - 10.1109/IJCNN.2009.5178680
DO - 10.1109/IJCNN.2009.5178680
M3 - Contribución a la conferencia
AN - SCOPUS:70449429572
SN - 9781424435531
T3 - Proceedings of the International Joint Conference on Neural Networks
SP - 1722
EP - 1729
BT - 2009 International Joint Conference on Neural Networks, IJCNN 2009
T2 - 2009 International Joint Conference on Neural Networks, IJCNN 2009
Y2 - 14 June 2009 through 19 June 2009
ER -