Realizing general MLP networks with minimal FPGA resources

Carl Latino, Marco A. Moreno-Armendáriz, Martin Hagan

Research output: Contribution to conferencePaperResearch

6 Citations (Scopus)

Abstract

In recent years, there has been significant interest in implementing neural networks on FPGAs. This paper describes a simple technique for implementing multi-layer neural networks, with arbitrary numbers of neurons and layers, on FPGAs, using minimal resources. The network architecture can be modified simply by loading memory with the architecture parameters and the network weights and biases. The paper also presents an application of the technology, in which a smart position sensor system is implemented with a neural network on a Xilinx Spartan 3E FPGA development system. ©2009 IEEE.
Original languageAmerican English
Pages1722-1729
Number of pages1549
DOIs
StatePublished - 18 Nov 2009
EventProceedings of the International Joint Conference on Neural Networks -
Duration: 1 Dec 2010 → …

Conference

ConferenceProceedings of the International Joint Conference on Neural Networks
Period1/12/10 → …

Fingerprint

Field programmable gate arrays (FPGA)
resources
Neural networks
Multilayer neural networks
Network architecture
Neurons
Data storage equipment
neurons
Sensors
sensors

Cite this

Latino, C., Moreno-Armendáriz, M. A., & Hagan, M. (2009). Realizing general MLP networks with minimal FPGA resources. 1722-1729. Paper presented at Proceedings of the International Joint Conference on Neural Networks, . https://doi.org/10.1109/IJCNN.2009.5178680
Latino, Carl ; Moreno-Armendáriz, Marco A. ; Hagan, Martin. / Realizing general MLP networks with minimal FPGA resources. Paper presented at Proceedings of the International Joint Conference on Neural Networks, .1549 p.
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Latino, C, Moreno-Armendáriz, MA & Hagan, M 2009, 'Realizing general MLP networks with minimal FPGA resources' Paper presented at Proceedings of the International Joint Conference on Neural Networks, 1/12/10, pp. 1722-1729. https://doi.org/10.1109/IJCNN.2009.5178680

Realizing general MLP networks with minimal FPGA resources. / Latino, Carl; Moreno-Armendáriz, Marco A.; Hagan, Martin.

2009. 1722-1729 Paper presented at Proceedings of the International Joint Conference on Neural Networks, .

Research output: Contribution to conferencePaperResearch

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Latino C, Moreno-Armendáriz MA, Hagan M. Realizing general MLP networks with minimal FPGA resources. 2009. Paper presented at Proceedings of the International Joint Conference on Neural Networks, . https://doi.org/10.1109/IJCNN.2009.5178680