TY - JOUR
T1 - Low voltage Lazzaro's WTA with enhanced loop gain
AU - Molinar-Solis, Jesus E.
AU - García-Lozano, Rodolfo
AU - Morales-Ramirez, Alejandra
AU - Espinoza-Ortega, Oscar
AU - Rocha-Perez, Miguel
AU - Diaz-Sanchez, Alejandro
AU - Ramirez-Angulo, Jaime
AU - Vazquez-Leal, H.
PY - 2012
Y1 - 2012
N2 - An additional stage for a Low Voltage Lazzaro's Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. Electrical measurements of a prototype in CMOS 0.5μm technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice and stability issues are presented as well.
AB - An additional stage for a Low Voltage Lazzaro's Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. Electrical measurements of a prototype in CMOS 0.5μm technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice and stability issues are presented as well.
KW - Low voltage
KW - Non-linear circuits
KW - Wta
UR - http://www.scopus.com/inward/record.url?scp=84864385683&partnerID=8YFLogxK
U2 - 10.1587/elex.9.648
DO - 10.1587/elex.9.648
M3 - Artículo
SN - 1349-2543
VL - 9
SP - 648
EP - 653
JO - IEICE Electronics Express
JF - IEICE Electronics Express
IS - 7
ER -