Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications

M. A. Pavanello; A. Cerdeira; M. A. Alemán; J. A. Martino; L. Vancaillie; D. Flandre

Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications

M. A. Pavanello, A. Cerdeira, M. A. Alemán, J. A. Martino, L. Vancaillie, D. Flandre

Research output: Contribution to conference › Paper › peer-review

Abstract

An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.

Original language	English
Pages	125-130
Number of pages	6
State	Published - 2005
Externally published	Yes
Event	207th ECS Meeting - Quebec, Canada Duration: 16 May 2005 → 20 May 2005

Conference

Conference	207th ECS Meeting
Country/Territory	Canada
City	Quebec
Period	16/05/05 → 20/05/05

Cite this

@conference{3cda7537474849408482f5c754dda7d5,

title = "Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications",

abstract = "An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.",

author = "Pavanello, {M. A.} and A. Cerdeira and Alem{\'a}n, {M. A.} and Martino, {J. A.} and L. Vancaillie and D. Flandre",

year = "2005",

language = "Ingl{\'e}s",

pages = "125--130",

note = "207th ECS Meeting ; Conference date: 16-05-2005 Through 20-05-2005",

}

TY - CONF

T1 - Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications

AU - Pavanello, M. A.

AU - Cerdeira, A.

AU - Alemán, M. A.

AU - Martino, J. A.

AU - Vancaillie, L.

AU - Flandre, D.

PY - 2005

Y1 - 2005

N2 - An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.

AB - An evaluation of the harmonic distortion in conventional and graded-channel SOI MOSFETs is performed from room temperature down to 90 K. The total harmonic distortion as a function of the transconductance over drain current ratio has been adopted as figure of merit. It is shown that the total harmonic distortion increases as the input voltage rises and the temperature is lowered. The use of lateral channel engineering in graded-channel transistors appreciably reduces the total harmonic distortion. The dependence of harmonic distortion on length of the lightly doped region is very weak.

UR - http://www.scopus.com/inward/record.url?scp=31844456723&partnerID=8YFLogxK

M3 - Artículo

SP - 125

EP - 130

T2 - 207th ECS Meeting

Y2 - 16 May 2005 through 20 May 2005

ER -

Low temperature and channel engineering influence on harmonic distortion of SOI nMOSFETs for analog applications

Abstract

Conference

Other files and links

Fingerprint

Cite this