Hardware-software platform for computing irreducible testors

Alejandro Rojas, René Cumplido, J. Ariel Carrasco-Ochoa, Claudia Feregrino, J. Francisco Martínez-Trinidad

Research output: Contribution to conferencePaper

8 Citations (Scopus)

Abstract

In pattern recognition, feature selection is a very important task for supervised classification. The problem consists in, given a dataset where each object is described by a set of features, finding a subset of the original features such that a classifier that runs on data containing only these features would reach high classification accuracy. A useful way to find this subset of the original features is through testor theory. A testor is defined as a subset of the original features that allows differentiating objects from different classes. Testors are very useful particularly when object descriptions contain both numeric and non-numeric features. Computing testors for feature selection is a very complex problem due to exponential complexity, with respect to the number of features, of algorithms based on testor theory. Hardware implementation of testor computing algorithms helps to improve their performance taking advantage of parallel processing for verifying if a feature subset is a testor in a single clock cycle. This paper introduces an efficient hardware-software platform for computing irreducible testors for feature selection in pattern recognition. Results of implementing the proposed platform using a FPGA-based prototyping board are presented and discussed. © 2011 Elsevier Ltd. All rights reserved.
Original languageAmerican English
Pages2203-2210
Number of pages1981
DOIs
StatePublished - 1 Feb 2012
Externally publishedYes
EventExpert Systems with Applications -
Duration: 1 Feb 2012 → …

Conference

ConferenceExpert Systems with Applications
Period1/02/12 → …

Fingerprint

Computer hardware
Feature extraction
Pattern recognition
Hardware
Field programmable gate arrays (FPGA)
Clocks
Classifiers
Processing

Cite this

Rojas, A., Cumplido, R., Ariel Carrasco-Ochoa, J., Feregrino, C., & Francisco Martínez-Trinidad, J. (2012). Hardware-software platform for computing irreducible testors. 2203-2210. Paper presented at Expert Systems with Applications, . https://doi.org/10.1016/j.eswa.2011.07.004
Rojas, Alejandro ; Cumplido, René ; Ariel Carrasco-Ochoa, J. ; Feregrino, Claudia ; Francisco Martínez-Trinidad, J. / Hardware-software platform for computing irreducible testors. Paper presented at Expert Systems with Applications, .1981 p.
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Rojas, A, Cumplido, R, Ariel Carrasco-Ochoa, J, Feregrino, C & Francisco Martínez-Trinidad, J 2012, 'Hardware-software platform for computing irreducible testors', Paper presented at Expert Systems with Applications, 1/02/12 pp. 2203-2210. https://doi.org/10.1016/j.eswa.2011.07.004

Hardware-software platform for computing irreducible testors. / Rojas, Alejandro; Cumplido, René; Ariel Carrasco-Ochoa, J.; Feregrino, Claudia; Francisco Martínez-Trinidad, J.

2012. 2203-2210 Paper presented at Expert Systems with Applications, .

Research output: Contribution to conferencePaper

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Rojas A, Cumplido R, Ariel Carrasco-Ochoa J, Feregrino C, Francisco Martínez-Trinidad J. Hardware-software platform for computing irreducible testors. 2012. Paper presented at Expert Systems with Applications, . https://doi.org/10.1016/j.eswa.2011.07.004