Hardware Design of Digital Parametric Conjunctors and t-Norms

This paper presents the hardware design and its implementation on FPGA of several parametric families of digital conjunctors and t-norms built from simple basic t-norms. The authors propose the method of unified presentation of the p-monotone sum, the simplified versions of the ordinal sum of t-norms and t-subnorms, and the method of extension of t-norms by the drastic t-norm. Such unification gives possibility to join several methods of construction of parametric digital conjunctors and t-norms in one scheme with the efficient FPGA implementation. The logic schemes of the proposed design are presented, and the comparative analysis of the latency time and the resources used for the implementation is given.