TY - GEN
T1 - FPGA implementation of parallel alpha-beta associative memories
AU - Aldape-Pérez, Mario
AU - Yáñez-Márquez, Cornelio
AU - Argüelles-Cruz, Amadeo José
PY - 2008
Y1 - 2008
N2 - Associative memories have a number of properties, including a rapid, compute efficient best-match and intrinsic noise tolerance that make them ideal for many applications. However, a significant bottleneck to the use of associative memories in real-time systems is the amount of data that requires processing. Notwithstanding, Alpha-Beta Associative Memories have been widely used for color matching in industrial processes [1], text translation [2] and image retrieval applications [3]. The aim of this paper is to present the work that produced a dedicated hardware design, implemented on a field programmable gate array (FPGA) that applies the Alpha-Beta Associative Memories model for fingerprint verification tasks. Along the experimental phase, performance of the proposed associative memory architecture is measured by learning large sequences of symbols and recalling them successfully. As a result, a simple but efficient embedded processing architecture that overcomes various challenges involved in pattern recognition tasks is implemented on a Xilinx Spartan3 FPGA.
AB - Associative memories have a number of properties, including a rapid, compute efficient best-match and intrinsic noise tolerance that make them ideal for many applications. However, a significant bottleneck to the use of associative memories in real-time systems is the amount of data that requires processing. Notwithstanding, Alpha-Beta Associative Memories have been widely used for color matching in industrial processes [1], text translation [2] and image retrieval applications [3]. The aim of this paper is to present the work that produced a dedicated hardware design, implemented on a field programmable gate array (FPGA) that applies the Alpha-Beta Associative Memories model for fingerprint verification tasks. Along the experimental phase, performance of the proposed associative memory architecture is measured by learning large sequences of symbols and recalling them successfully. As a result, a simple but efficient embedded processing architecture that overcomes various challenges involved in pattern recognition tasks is implemented on a Xilinx Spartan3 FPGA.
KW - Associative memories
KW - FPGA
KW - Fingerprint
KW - Pattern recognition
KW - Reconfigurable logic
UR - http://www.scopus.com/inward/record.url?scp=47749155278&partnerID=8YFLogxK
U2 - 10.1007/978-3-540-69812-8_108
DO - 10.1007/978-3-540-69812-8_108
M3 - Contribución a la conferencia
SN - 3540698116
SN - 9783540698111
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 1081
EP - 1090
BT - Image Analysis and Recognition - 5th International Conference, ICIAR 2008, Proceedings
T2 - 5th International Conference on Image Analysis and Recognition, ICIAR 2008
Y2 - 25 June 2008 through 27 June 2008
ER -